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Method for biasing a differential pair of transistors, and corresponding integrated circuit

A technology of integrated circuits and transistors, which is applied in the field of integrated circuits of differential pair MOS transistors, and can solve problems such as affecting the performance of differential pairs.

Pending Publication Date: 2020-12-11
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] The above drawbacks adversely affect the performance of the differential pair with respect to input voltage dynamics, especially when transitioning from an n-type differential pair to a p-type differential pair (and vice versa), and are present regardless of the adjusted compensation value

Method used

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  • Method for biasing a differential pair of transistors, and corresponding integrated circuit
  • Method for biasing a differential pair of transistors, and corresponding integrated circuit
  • Method for biasing a differential pair of transistors, and corresponding integrated circuit

Examples

Experimental program
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Embodiment Construction

[0051] Each transistor NP, NM of the differential pair is controlled by a corresponding input signal INP, INM on its gate. Transistor NP is positioned at the positive input INP and transistor NM is positioned at the negative input INM.

[0052] The sources of the differential pair transistors NP, NM are connected to a bias node Nd via respective resistive elements R1, R2. The corresponding resistance elements R1, R2 have the same resistance value.

[0053] The drains of transistors NP, NM each form a respective output of the differential pair.

[0054] The integrated circuit CI comprises a bias current generator GIDiff configured to generate a bias current 2*Idiff that is applied to the bias node Nd.

[0055] Therefore, the transistors NP, NM are biased in a balanced manner and have the same differential current Idiff for each channel. The output voltage on the transistor drain varies depending on the conduction of the corresponding transistor NP, NM, depending on the input...

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Abstract

An embodiment of the disclosure relates to a method for biasing differential pair transistors and a corresponding integrated circuit. The integrated circuit includes at least one differential pair oftransistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of thethreshold voltages of the transistors of said differential pair.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French application No. 1906167 filed on June 11, 2019, which is hereby incorporated by reference. technical field [0003] Embodiments and implementations relate to integrated circuits, particularly integrated circuits including differential pair MOS transistors. Background technique [0004] Integrated comparator and amplifier devices typically include a differential pair of MOS transistors that are biased by a bias current. The respective conduction of the transistors controlled by the respective input signals allows comparing or amplifying differences in the input voltages. [0005] In a comparator, the transistors must respond in the same way for the comparison to be accurate. Therefore, the threshold voltages of transistors in a differential pair must be equal. In practice, the actual threshold voltages of transistors vary systematically between them due to manufacturing c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/30H03K17/16
CPCH03K17/302H03K17/161H03K5/003H03K3/3565H03K5/08H03K5/24H03K3/22H03F3/45076H03K17/56
Inventor Y·若利V·比内M·屈埃卡
Owner STMICROELECTRONICS (ROUSSET) SAS