Method and apparatus for access line management of memory cell arrays
A technology of memory unit and access line, which is applied in the direction of static memory, digital memory information, information storage, etc.
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[0018] Some memory arrays may include a plate that is common to multiple memory cells that are also associated with multiple digit lines and / or multiple word lines. Because the voltage of the plate (and thus also the voltage of the associated plate line) fluctuates (eg, between a high voltage and a low voltage) in relation to the access operation for the selected memory cell, some memory devices may use the Each word line of unselected memory cells common to the panel (which may be referred to as an unselected word line) is maintained at a fixed voltage. This may result in leakage currents and associated Link power loss. Where a plate is common to many memory cells, the amount of capacitance (e.g., parasitic capacitance) and unintended cross-coupling between the plate and unselected word lines can be significant, and thus, the amount of associated power loss can be significant . Parasitic signals due to such unintended cross-coupling, along with additional power consumption...
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