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Test resource scheduling management method suitable for radio frequency chip parallel test

A technology of radio frequency chips and testing resources, which is applied in fault hardware testing methods, faulty computer hardware detection, electrical digital data processing, etc. Software design difficulty, simplified software complexity, and the effect of high hardware resource utilization

Inactive Publication Date: 2020-12-18
CHINA ELECTRONIS TECH INSTR CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Traditional testing generally uses two methods to achieve parallel testing. The first method is to pile up multiple sets of hardware resources and schedule a single set of software. This method has obvious resource waste problems.
The second method is a single set of hardware resources, and a single set of software is dynamically scheduled in real time. This method often has problems such as high software complexity, high maintenance costs, and uncontrollable test index dependencies.
Various problems make parallel testing more difficult and costly

Method used

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  • Test resource scheduling management method suitable for radio frequency chip parallel test
  • Test resource scheduling management method suitable for radio frequency chip parallel test

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Embodiment Construction

[0019]The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0020]The present invention provides a test resource scheduling management method suitable for parallel testing of radio frequency chips, including the following processes:

[0021](1) First, divide the index system according to the hardware resources required by the radio frequency chip test index, so that there is no coupling between the hardware of each index system. The index system in this embodiment includes a spectrum index system, a power index system, a noise index system, and S parameters. Index system and power consumption index system, a total of 5 index systems.

[0022](2) Take each index system as the test node to form a test sequence loop, such asfigure 1 As shown, and each test node has its own system lock, specifically including spectrum lock, power lock, noise lock, S parame...

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Abstract

The invention discloses a test resource scheduling management method suitable for a radio frequency chip parallel test. The method comprises the following steps: (1) firstly, carrying out index systemdivision; (2) forming a test sequence ring by taking each index system as a test node, wherein each test node is provided with a respective system lock; (3) starting a test thread from each differenttest node at the same time; (4) the test thread immediately releasing a system lock after completing the index system test of the current test node, wherein other test threads can perform locking test on the released index system again; and (5) sequentially completing the test of each index system by each test thread along the same direction of the test sequence ring. According to the method disclosed by the invention, test resources are recycled and used in a staggered manner, high-speed parallel test of a radio frequency chip can be realized, the hardware resource utilization rate is extremely high while the software design difficulty is reduced, and the method has the characteristics of convenient development and maintenance process, low resource cost and the like.

Description

Technical field[0001]The invention relates to a test resource scheduling management method, in particular to a test resource scheduling management method suitable for parallel testing of radio frequency chips.Background technique[0002]Radio frequency chips are a type of chip commonly used in industrial design and production processes, and are in great demand by society. In order to ensure chip indicators, the chip needs to be tested in detail before leaving the factory. Take a radio frequency power amplifier chip as an example. The test indicators generally include input and output standing wave, gain, compression point, power, efficiency, etc. During the testing process, multiple sites are generally required for parallel testing, which requires high testing efficiency.[0003]Traditional testing generally uses two methods to achieve parallel testing. The first method is stacking multiple sets of hardware resources and single set of software scheduling. This method has obvious resourc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F11/22
CPCG06F9/4843G06F9/4806G06F11/2273
Inventor 徐宝令阎涛张海庆乔宏志徐瑞杰苗继超
Owner CHINA ELECTRONIS TECH INSTR CO LTD
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