Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for manufacturing chip packaging structure

A technology of chip packaging structure and manufacturing method, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc. Connection reliability issues, effect of warpage reduction

Active Publication Date: 2020-12-22
SIPLP MICROELECTRONICS CHONGQING CO LTD
View PDF6 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product
[0003] However, the production efficiency of the existing chip packaging is low, and the performance of the packaging structure is not reliable

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for manufacturing chip packaging structure
  • Method for manufacturing chip packaging structure
  • Method for manufacturing chip packaging structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0068] figure 1 It is a flowchart of a manufacturing method of a chip package structure according to an embodiment of the present invention. Figure 2 to Figure 6 yes figure 1 The schematic diagram of the intermediate structure corresponding to the process in .

[0069] First, refer to figure 1 Step S01 in figure 2 As shown, a multi-chip packaging structure 10 is provided. The multi-chip packaging structure 10 includes a first plastic encapsulation layer 100 and a plurality of dies 101 embedded in the first plastic encapsulation layer 100. Each die 101 includes a front side 101a and a back side 101b, the front side 101a has an electrical interconnection structure (not shown); the front side 101a is exposed to the outside of the first plastic encapsulation layer 100 .

[0070] Next, refer to figure 1 Step S02 in image 3 As shown, the external leads 11 are formed on the front side 101 a of each die 101 in the multi-die package structure 10 .

[0071] After that, refer to ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for manufacturing a chip packaging structure, and the method comprises the steps: dividing a multi-crystal-grain packaging structure into a plurality of regions, and enabling each region to comprise a plurality of crystal grains; and when a second plastic packaging layer for embedding the outer pins is formed on the crystal grain packaging structure, curing the second plastic packaging layer by using a multi-cavity mold with a partition plate. The multi-cavity mold can reduce the curing shrinkage range of the second plastic package layer from one whole block toa plurality of small blocks, so that the shrinkage stress is reduced exponentially due to the reduction of the shrinkage range when the liquid plastic package material is cured, the warping degree ofthe multi-grain package structure is reduced, and the problem of the electrical connection reliability of the outer pins can be improved.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a method for manufacturing a chip packaging structure. Background technique [0002] In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high performance and high reliability. Packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product. [0003] However, the production efficiency of the existing chip packaging is low, and the performance of the packaging structure is not reliable. [0004] In view of this, the present invention provides a new manufacturing method of a chip packaging structure to solve the above technical problems. Contents of the invention [0005] The object of the present invention is to provide a method for manufacturing a chip packaging structure, which imp...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/56H01L21/60
CPCH01L21/561H01L21/565H01L24/03H01L2224/18H01L2224/96
Inventor 周辉星
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com