FPGA-based multivariate LDPC high-speed decoder and decoding method

A decoder and multiple technologies, applied in the field of communication and channel coding, to achieve high decoding accuracy, reduce computational complexity, and lower requirements

Pending Publication Date: 2021-01-01
SHENZHEN ACAD OF AEROSPACE TECH +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The EMS algorithm reduces the decoding complexity from qlog 2 q is reduced to n m log 2 no m , but from the perspective of hardware, the complexity of the EMS algorithm is still n m 2 Magnitude

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  • FPGA-based multivariate LDPC high-speed decoder and decoding method
  • FPGA-based multivariate LDPC high-speed decoder and decoding method
  • FPGA-based multivariate LDPC high-speed decoder and decoding method

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Embodiment Construction

[0061] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0062] In the description of the present invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc. indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only In order to facilitate the description of the present invention and simplify the description, it does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific ...

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Abstract

The invention discloses an FPGA-based multivariate LDPC high-speed decoder and a decoding method, and the decoder comprises a control module which is used for controlling the state transition of the decoder; a message storage module which is used for storing channel initial information and intermediate messages; a check node updating module which is used for updating a check node, carrying out inverse permutation on domain elements and operating an extended mini-sum decoding algorithm based on a bubble algorithm; a variable node updating module which is used for updating variable nodes in parallel on the basis of the row-column structure of a check matrix; and an initial replacement module which is used for completing the first replacement operation of the domain elements, wherein the restreplacement processes are completed in the variable node updating module. According to the decoder, hardware implementation of the decoder is carried out by using the extended mini-sum decoding algorithm based on the bubble algorithm, so that the decoder can reduce the operation complexity while ensuring high decoding accuracy, and the decoder can be widely applied to the technical field of channel coding in the communication field.

Description

technical field [0001] The invention relates to the technical field of channel coding in the communication field, in particular to an FPGA-based multivariate LDPC high-speed decoder and a decoding method. Background technique [0002] With the continuous advancement of modern communication technology and the development of 5G mobile communication, the communication system is developing towards large capacity, high availability and high throughput. As the currently proposed channel coding method whose performance is closest to the Shannon limit, LDPC codes are playing an important role. The multivariate non-binary LDPC code provides higher coding gain than the binary LDPC code, and performs better in resisting burst errors, and is more suitable for systems with high frequency band utilization. [0003] In recent years, multivariate LDPC codes have attracted the attention of the academic community due to their many advantages. At the same time, due to the high complexity of e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/116
Inventor 于波闫泽涛
Owner SHENZHEN ACAD OF AEROSPACE TECH
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