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Apparatus and method for efficient parallel computation

A technology of parallel computing and computing units, applied in the field of parallel processing systems that improve efficiency, and can solve problems such as low efficiency

Pending Publication Date: 2021-01-01
PARTEC CLUSTER COMPETENCE CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The downside is that most data-intensive applications will a priori achieve η below 5% to 10% on current CPUs A and about 15% of η on current GPUs A , regardless of any further reduction due to the algorithm being executed or parallelism in terms of required processing elements
For a given R of processing elements, the more data-intensive the application, the efficiency η A become lower

Method used

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  • Apparatus and method for efficient parallel computation
  • Apparatus and method for efficient parallel computation
  • Apparatus and method for efficient parallel computation

Examples

Experimental program
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Embodiment Construction

[0034] The present invention can be implemented using existing technologies. For example, it could be a way to accelerate the performance of applications in booster modules within a modular supercomputing system targeting peak exascale performance by 2021, as described in WO 2012 / 049247 A1 and in subsequent applications EP 16192430.3 and EP18152903.3, which are hereby incorporated by reference for all purposes. The goal of the present invention is to improve node application performance in computation by a factor f for data-intensive computations as compared to any other architectural design, and additionally, to increase communication bandwidth to be in sync with memory bandwidth to better scale non-trivial architectures with large communication requirements. Many applications of compute nodes.

[0035] The implementation is given by a set of compute nodes using Mellanox BlueField (BF) multi-core system-on-chip technology. BlueField cards can include multiple graphics proc...

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Abstract

The present invention provides a computing unit for operating in a parallel computing system, the computing unit comprising a plurality of processing elements and an interface for connecting the computing unit to other components of the computing system wherein each processing element has a nominal maximum processing rate NPR and each processing element includes a respective memory unit such thatdata can be transferred from the memory unit at a predetermined maximum data rate MBW and the interface provides a maximum data transfer rate CBW, wherein in order to provide a predetermined peak calculation performance for the computing unit PP obtainable by a number n processing elements operating at the nominal maximum processing rate such that PP = n * NPR operations per second, the computingunit includes an integer multiple f times n processing elements wherein f is greater than one and each processing element is limited to operate at a processing rate of NPR / f.

Description

technical field [0001] The present invention relates to parallel processing systems, and in particular to parallel processing systems with improved efficiency in terms of performance / power consumption. Background technique [0002] In a typical parallel processing system, multiple computing nodes, each including one or more processing elements, are connected by a high-speed network. The processing elements of the compute nodes each have internal memory. Processing elements are connected within their compute nodes. The connectivity of the nodes in the computation can be achieved using high-speed networks, high-speed networks of separate nodes in the computation, or common memory (as for example in symmetric multiprocessing SMP systems). This arrangement is shown in the figure 1 middle. [0003] figure 1 An arrangement of a plurality of computing nodes CN is shown, where each computing node comprises a plurality of processing elements PE each with a corresponding memory M...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F1/324G06F1/329G06F1/3296
CPCG06F1/324G06F1/329G06F1/3296G06F9/5094Y02D10/00G06F9/4893G06F9/5027
Inventor B·福罗维特T·利珀特
Owner PARTEC CLUSTER COMPETENCE CENT