Write-blocking type communication control method and component between processor and memory, equipment and medium

Abstract

The invention discloses a write-blocking type communication control method and component between a processor and a memory, equipment and a medium, which are used for differently processing a memory access request which needs to be sent to an off-chip memory by the processor and a read response from the off-chip memory; storing a target address of a read request into a storage table and setting itto be valid, sending to a request sending command request queue to queue and send to the off-chip memory; if the read response contains an uncorrectable error, resending a read request corresponding to the read response to the off-chip memory, otherwise, setting the target address of the read response to be invalid in the storage table, and returning the read response; and selecting whether to block a write request in the storage table according to whether the target address of the write request exists in the storage table, and stopping blocking the write request when the target address of thewrite request becomes invalid in the storage table. System performance is not influenced as much as possible, and the inter-board soft error between the main processor and the off-chip memory can beaccommodated at the maximum probability.

Description

Technical field[0001]The present invention relates to a high-performance processor, in particular to a write blocking communication control method, component, equipment and medium between the processor and the memory.Background technique[0002]In the current mainstream design of high-performance processors, the communication between the processor and the off-chip memory is completed through the motherboard. The most common way is for the processor to follow the DDR protocol to issue memory access read and write commands and write data including memory addresses. The motherboard transmits to off-chip content; off-chip memory follows the DDR protocol and returns the read response data to the processor through the motherboard. In the DDR protocol, technologies such as ODT (On-DieTermination, on-chip termination) are used to solve the crosstalk and reflection between signals. However, with the development of technology, the reduced power supply voltage and high clock frequency aggravate ...

AI Technical Summary

Problems solved by technology

Therefore, the write request will cause some inter-board soft errors that cannot be tolerated

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