A Multi-platform Linkage Efficiency Improvement Mechanism

Abstract

The present invention provides a multi-platform linkage efficiency improvement mechanism, including a probe station, at least two testing machines, and a control system; wherein, the control system includes a signal configuration unit and a path planning unit, and the signal configuration unit It is set independently, and is respectively connected with the probe station and the test machine through GPIB ports to realize the signal transmission between the probe station and the test machine. By setting up an independent signal configuration unit, using the GPIB port to collect the signal information of the mutual communication between the probe station and the test machine to the main control board, the program module of the main control chip splits and merges the signals, which can be more flexible Use testing machine configuration; path planning unit can generate and control the path strategy related to the moving path of the probe station carrying the wafer to be tested, so as to control the carrier of the probe station to execute the path strategy, and complete the The wafer to be tested moves in different poses to improve the efficiency of the test.

Description

technical field [0001] The invention relates to the field of semiconductor testing equipment, in particular to a multi-platform linkage efficiency-raising mechanism for probe station signal configuration. Background technique [0002] In integrated circuit testing, usually a testing machine is connected to a probe station for testing. At this time, the test machine and the probe station are directly connected, and communicate with each other through the original communication protocol of the two. The test machine asks a message, and the probe station answers a message, and only one-to-one access is possible. This testing method greatly limits the efficiency of the testing machine, and causes a great waste of testing time and layout of the probe card. Since the maximum number of configurations of a test machine is fixed, the test channels it can support are also fixed, but the number of test terminals of the probe card is also limited accordingly, and there is no way to reac...

AI Technical Summary

Problems solved by technology

[0006] And each testing machine needs to keep the poses of the wafer to be tested differently during the testing process, therefore, the carrier carrying the wafer to be tested moves the wafer to be tested from the The time required to convert the required pose to the test pose required by another testing machine determines the final test time required to complete the wafer to be tested, and also affects the efficiency of the test

In the patent with the authorized announcement number CN103777131B, although one probe station can connect multiple testing machines, the moving path of the probe platform during the movement is the same as the path when the probe station is connected to a single testing machine.

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