Logic resource evaluation method

Abstract

The invention discloses a logic resource evaluation method. The method comprises the steps of obtaining a to-be-estimated related feature list; inputting the to-be-estimated related feature list intoan FPGA resource model to obtain an FPGA resource usage amount estimated value, the FPGA resource model being obtained by training by using a training data list based on a to-be-trained model, the training data list being a set of a feature training list and a resource usage amount data training list, and the feature training list being a set of RTL description related training features and designparameter related training features. According to the FPGA resource model obtained through the method, the on-chip resource usage amount needed by RTL description can be rapidly obtained at the initial stage of design, the estimability of design and logic synthesis is enhanced, and the number of iterations is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a logic resource evaluation method. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is an important semiconductor device, which can realize the logic design required by users through on-site reprogramming. When the designer uses the hardware description language to program the register transfer level (RTL) of the circuit, the RTL description will be converted into bit stream data for configuring the internal structure of the FPGA through multiple design synthesis steps. These design synthesis steps include Logic synthesis, technology mapping, logic packaging, place and route, and more. [0003] At this stage, for a given RTL description, the number of FPGA on-chip hardware resources required by it generally requires the completion of logic packaging and routing before the full number of resources can be obtaine...

AI Technical Summary

Problems solved by technology

When the problem of insufficient on-chip resources occurs, the designer needs to modify the RTL description and perform time-consuming design synthesis process iterations

[0004]Because the design synthesis process includes multiple steps, when the designer writes and modifies the RTL description, he cannot quickly predict the amount of on-chip hardware resources required for the circuit to be implemented on the FPGA. This can result in technology mapping not being done or routing not being done and resulting in multiple design iterations

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