Reconfigurable general standard convolution accelerator design method based on HLS

Abstract

The invention discloses an HLS-based reconfigurable general standard convolution accelerator design method, which comprises the following steps: analyzing standard convolution calculation characteristics to obtain parallelism of four scales including convolution kernel, feature map, convolution kernel and feature map, and performing parallelization design on convolution calculation by using a cyclic partitioning and cyclic expansion technology to obtain a reconstructed general standard convolution accelerator. Introducing a cyclic blocking factor to control a parallelization scale; a weight bias storage structure, a feature map row cache structure and a multi-stage output cache structure are designed for on-chip storage of an accelerator, and a multi-channel parallel read-write structure is designed by using an AXI4 bus; for 3 * 3 and 1 * 1 convolution calculation, a reusable convolution calculation method is designed, and hardware resources are effectively saved; a five-layer streamlined structure is designed for the calculation process of the convolution layer, and the convolution calculation efficiency is improved.

Description

technical field [0001] The invention relates to the field of hardware accelerator design for convolution calculation in convolutional neural networks, in particular to an HLS-based reconfigurable general standard convolution accelerator design method. Background technique [0002] Convolutional neural networks are more and more applied to real life, and their practical application value is constantly being highlighted. They have very important applications in various fields such as image classification, target detection, semantic segmentation, and speech recognition. . With the continuous wave of artificial intelligence, various advanced algorithms emerge in an endless stream, in the field of image classification: AlexNet, VGG, ResNet, GoogleNet, etc., in the field of target detection: R-CNN, Faster R-CNN, SSD, YOLO, etc., The accuracy of the network is getting higher and higher, but the structure of the network is becoming more and more complex, and the scale of the networ...

AI Technical Summary

Problems solved by technology

With the continuous wave of artificial intelligence, various advanced algorithms emerge in an endless stream, in the field of image classification: AlexNet, VGG, ResNet, GoogleNet, etc., in the field of target detection: R-CNN, Faster R-CNN, SSD, YOLO, etc., The accuracy of the network is getting higher and higher, but the structure of the network is becoming more and more complex, and the scale of the network is getting larger and larger, so the network training and the network feed-forward process after the training is completed become very slow.

Large-scale networks rely on GPU servers for network computing, but for mobile and edge devices, the network structure is very large, making it difficult to realize the practical application of embedded devices

In addition, relying on the continuous improvement of chip manufacturing technology, the performance of CPU and GPU is continuously improved, and there are also various chips for the embedded field, such as Nvidia's TX1 and TX2, which have relatively good performance and power consumption, but Its power consumption and size are still relatively large, which cannot meet the urgent needs of the current industry

[0003] For the acceleration of network-related models using FPGA, as early as 1996, Cloutier and others began to study the acceleration of convolutional neural networks using FPGA. They realized the related design of handwritten letter recognition on FPGA, which was limited by the chip manufacturing process at that time. , the resource density on the FPGA chip is very low, and the parallelism of the convolutional neural network has not been fully designed, so no good experimental results have been obtained in the end, and the network execution speed is slow (article title: Vip: An fpga-based processor for image processing and neural networks; conference: In FifthInternational Conference on Microelectronics for Neural Networks and FuzzySystems (MicroNeuro'96), Lausanne, Switzerland; author: Cloutier J, Cosatto E, PigeonS, et al.; publication year: 1996; page number: 330 -336)

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