Memory and neuromorphic chip
A memory and chip technology, applied in static memory, digital memory information, information storage, etc., to achieve the effect of increasing storage duration, flexible data storage duration, and adjusting data storage duration
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Embodiment 1
[0029] figure 1 It is a schematic structural diagram of a memory in Embodiment 1 of the present invention, which can be applied to any device, for example, a neuromorphic chip, a traditional chip, and the like. Such as figure 1 As shown, the memory 10 provided in this embodiment includes: a connected non-volatile memory unit 100 and a refresh circuit 200 . Wherein, the refresh circuit 200 is used for reading the storage data in the non-volatile storage unit 100 and writing the storage data back to the non-volatile storage unit 100 .
[0030] The non-volatile memory unit 100 may include but not limited to one or more of FLASH flash memory, phase change memory, ferroelectric memory FRAM, resistive memory RRAM, magnetic memory MRAM, spin memory STT-RAM and optical memory .
[0031] The refresh circuit 200 is used to refresh the stored data in the non-volatile memory unit 100, read the stored data in the non-volatile memory unit 100, and write the read stored data back to the n...
Embodiment 2
[0061] Figure 4 It is a schematic structural diagram of a neuromorphic chip in Embodiment 2 of the present invention, which is applicable to neural network computing. Such as Figure 4 As shown, the neuromorphic chip 1 provided in this embodiment includes: at least one memory 10 described in any embodiment of the present invention (one memory 10 is shown in the figure).
[0062] have to be aware of is, Figure 4 The shown neuromorphic chip is only an example showing that the neuromorphic chip includes the memory 10 and the neuron computing core 50 , and does not specifically limit the structure of the neuromorphic chip.
[0063] Optionally, one neuromorphic chip 1 may include one or more memories 10 . When a neuromorphic chip 1 includes only one memory 10 of the disclosed embodiment, the stored data in the memory 10 can be shared by multiple neuron computing cores; when a neuromorphic chip 1 includes multiple memories 10 , the stored data in each memory 10 can be used ind...
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