Side channel attack resisting method for SoC security chip and side channel attack resisting electronic system
A security chip and channel attack technology, applied in the protection of internal/peripheral computer components, etc., can solve the problem of not being able to balance the security protection capability of SoC security chips and the speed of cryptographic operations, and improve the ability to resist side channel attacks and similarity. High, enhance the effect of side channel attack
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Embodiment 1
[0044] This embodiment provides a SoC security chip anti-side channel attack method, such as figure 1 As shown, each time the plaintext data to be processed is received, a cryptographic operation is performed on the plaintext data to be processed, and each cryptographic operation includes two cryptographic operations, specifically including the following steps:
[0045] Step S101, setting N types of true and false combination modes of the password parameters of the current cryptographic operation, the N types of true and false combination modes include: the combination mode in which the password parameters of the two cryptographic operations are all true, the combination mode of the two cryptographic operations There is at least one of the combination modes in which at least one parameter is false in the password parameters, and in the combination mode in which all the password parameters of one cryptographic operation are true and at least one parameter in the password paramet...
Embodiment 2
[0060] On the basis of the above embodiments, the embodiment of the present invention provides another SoC security chip anti-side channel attack method, such as figure 2 As shown, the difference from the above embodiment is that this embodiment further optimizes the operation process of each cryptographic operation in step S103, so as to make the energy trace of the SoC security chip more confusing, specifically including:
[0061] S201: Generate an IP core state control random number R1, and write R1 into the IP core state control register in the SoC security chip, activate the IP core whose state bit is "1" in the IP core state control register and perform this password For the IP core of the operation, turn off the IP core whose status bit is "0" to generate random power consumption;
[0062] Specifically, the SoC security chip is integrated with IP cores with multiple functions. For example, GPIO general input / output IP core, URAT serial communication IP core, EMM memor...
Embodiment 3
[0079] An embodiment of the present invention provides a SoC security chip anti-side-channel attack method. After each plaintext data to be processed is received, at least one cryptographic operation is performed on the plaintext data to be processed, and each cryptographic operation includes L passwords. Operation, L is greater than 2;
[0080] The difference from each round of cryptographic operations including two cryptographic operations is that if the combination of authenticity and falsehood determined according to R0 is: the cryptographic parameters of each cryptographic operation in this round of cryptographic operations are all true, then continue to judge the pending Whether the length of the plaintext data is greater than L times the length of the plaintext data required for a cryptographic operation, if so, add a false operation between any two true operations, otherwise re-execute step S102.
[0081] For example, if L=3, the password parameters of the three crypto...
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