Method for forming thin film layer in deep hole and method for manufacturing semiconductor device

Abstract

The invention provides a method for forming a thin film layer in a deep hole, the method comprising: providing a substrate formed with the deep hole and placing the substrate into a deposition chamber; introducing a reaction into the deposition chamber by using an atomic layer deposition process source for a certain period of time; stop feeding the reaction source into the deposition chamber, and seal the deposition chamber for a certain period of time to form a film layer on the sidewall of the deep hole. The advantage of the present invention is that after the reaction source is stopped feeding into the deposition chamber, the deposition chamber is sealed for a certain period of time, so that the reaction source not participating in the reaction stays in the deposition chamber. After the deposition chamber is sealed, a high-pressure environment is formed in the deposition chamber, and under the action of pressure, the unreacted reaction source will flow toward the bottom of the deep hole, so that no deposition occurs at the bottom of the deep hole. area deposition, and the reaction source can be evenly distributed, thereby forming a film with uniform thickness and high quality in the deep hole.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a method for forming a thin film layer in a deep hole and a method for preparing a semiconductor device. Background technique [0002] NAND storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices are close to the limit of practical expansion. In order to further increase storage capacity and reduce storage cost per bit, 3D NAND storage devices are proposed. [0003] In 3D NAND storage devices, the method of vertically stacking multi-layer gates is adopted. The central area of ​​the stacked layer is the core storage area, and the edge area is a stepped structure. The core storage area is used to form the memory cell string, and the conductive layer in the stacked layer is used as The gate lines of the memory cells in each layer are dra...

AI Technical Summary

Problems solved by technology

However, more stacking layers of 3D NAND memory devices make the production process face more severe challenges. For example, the aspect ratio of deep holes such as channel holes (Channel Hole) is large, and the film deposition in deep holes will have uneven thickness.

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