Operation address determination method, PCIe system, electronic equipment and storage medium

Abstract

The invention discloses an operation address determination method, a PCIe system, electronic equipment and a computer readable storage medium. The method comprises the steps: by a PCIe host, acquiringan operation address; generating a target base address and a target offset address corresponding to the operation address based on the offset address block information; generating a register settinginstruction based on the target base address and the target offset address; and sending the register setting instruction to PCIe equipment so as to set a first register used for storing the target base address and / or a second register used for storing the target offset address in the PCIe equipment. The method comprises the following steps: dividing the operation address in the PCIe equipment intoa plurality of offset address blocks by utilizing the target base address and the target offset address; the size of the data space required for recording the target base address and the target offset address is far less than the length of the full address space, so that the PCIe host can control and access the PCIe equipment without limitation.

Description

technical field [0001] The present application relates to the technical field of device control, in particular to a method for determining an operation address, a PCIe system, an electronic device, and a computer-readable storage medium. Background technique [0002] PCIe is a high-speed serial computer expansion bus standard and a high-speed serial bus commonly used in the industry. The PCIe host (ie, the host side) and the PCIe device (ie, the device side) can use the PCIe bus to communicate. In related technologies, the host side writes specific operation addresses into a continuous address space located in the device side, so that the device side knows the operation addresses to be operated, and then controls the device side to perform corresponding operations. However, in order to prevent the continuous address space that needs to be allocated on the device side from exceeding the address space that can be allocated by the system, resulting in abnormal address allocati...

AI Technical Summary

Problems solved by technology

However, in order to prevent the continuous address space that needs to be allocated on the device side from exceeding the address space that can be allocated by the system, resulting in abnormal address allocation, the continuous address space is usually set smaller in the related art

The smaller continuous address space allows the host to only write fewer operating addresses, resulting in greater restrictions on the host's control and access to the device, which in turn limits the use of PCIe hosts and PCIe devices. Therefore, Related technologies have significant limitations

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