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Semiconductor device mount structure and semiconductor device mount method

A technology for semiconductors and devices, applied in the field of semiconductor device assembly and structure, can solve the problems of unfavorable reliability, high cost and influence of packaging

Inactive Publication Date: 2003-10-15
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As described above, in the prior art, the above-mentioned terminals are formed on the circuit plane of the semiconductor device, so there is a problem in the prior art that the terminals on the circuit plane of the semiconductor device have an adverse effect on the reliability of the package
However, this method requires a long time and a high cost, and it is necessary to increase the temperature of the package to the melting point of the solder when the package is mounted on or removed from the substrate.
In this way, the heating of the package itself will increase, and this increase will have an adverse effect on the reliability of the package.

Method used

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  • Semiconductor device mount structure and semiconductor device mount method
  • Semiconductor device mount structure and semiconductor device mount method
  • Semiconductor device mount structure and semiconductor device mount method

Examples

Experimental program
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Embodiment 1

[0040] FIG. 1 is a sectional view showing a semiconductor device mounting structure of Embodiment 1 of the present invention.

[0041] Referring to Fig. 1, the semiconductor device assembly structure of embodiment 1 of the present invention has: semiconductor device 10; Be positioned at the connection substrate 30 of the below of semiconductor device; Lead 20, this lead is designed to bend back (for example, bend into U-shape) One end of each lead is connected to the external connection electrode 12 of the semiconductor device 10 , and the other end is connected to the mounting electrode 40 on the connection substrate 30 .

[0042]The connection substrate 30 is designed such that the main surface or main plane of the connection substrate 30 having the mounting electrodes 40 thereon does not face the circuit surface or the circuit plane of the semiconductor device 10 . Further, wirings connected to the mount electrodes 40 are formed on the main plane of the connection substrate...

Embodiment 2

[0068] Next, Embodiment 2 of the present invention will be described in detail with reference to the drawings. The second embodiment is characterized in that an insulating sheet 70 is provided between the connection substrate 30 and the circuit plane 11 of the semiconductor device 10 . The rest of the constitution is the same as in Embodiment 1.

[0069] see Figure 11A and Figure 11B. The insulating sheet 70 is formed between the circuit plane 11 and the connection substrate 30 of the semiconductor device 10 , and touches each circuit plane 11 and the connection substrate 30 . The insulating sheet 70 is designed to have such a thickness that when each of the carrier substrates 31, 32, 33 and 34 constituting the connection substrate 30 is bent toward the circuit plane of the semiconductor device 10, The assembly plane formed by and 34 is a plane.

[0070] The above-mentioned insulating sheet 70 is desirably formed of a silicon rubber sheet, because the silicon rubber she...

Embodiment 3

[0077] Next, Embodiment 3 of the present invention will be described in detail. Embodiment 3 is characterized in that there is a connection substrate at the lower part of the lead. The rest of the composition is the same as in Embodiment 1.

[0078] see Figure 12 . At the lower portion of the lead wire 20 there is a connection substrate 80 . That is, the outer lead portion 23 of each lead 20 is connected to a main plane different from the mounting plane of the connection substrate 80 . The connection substrate 80 is composed of the following parts: electrodes connected to the outer lead portion 23; through holes 81 connected to the electrodes and penetrating the connection substrate 80; connected to the through holes 81 and formed on the connection substrate 80 a wiring 82 on the mounting plane; and a plurality of mounting electrodes 41 connected to the wiring 82 . Each of the plurality of mount electrodes 41 is electrically connected to the lead 20 through the through h...

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Abstract

A semiconductor device mount structure containing a semiconductor device (10), a connection substrate (30) disposed at the lower side of the semiconductor device (10), and leads (20) which are connected to external connection terminals (12) of the semiconductor device (10) at one end thereof, turned back and connected to wires provided on the connection substrate (30) at the other end thereof. The connection substrate (30) is constructed by plural carrier substrates. Each of the plural carrier substrates is right-angled isosceles triangular, and the plural carrier substrates are arranged so as to form a substantially square shape at the lower portion of the semiconductor device (10).

Description

technical field [0001] The present invention relates to a semiconductor device mounting structure and a semiconductor device mounting method, in particular to a semiconductor mounting structure on which a semiconductor device can be mounted, and the size of the structure is substantially the same as that of the semiconductor device. Background technique [0002] This type of semiconductor device has been disclosed in Japanese Unexamined Patent Application Laid-Open No. Hei 7-509352. [0003] In the semiconductor device mounting structure disclosed in the above publication, a slit is formed in the wafer support structure to divide the support structure into the central portion and the outer fixing member through the slit. The central portion is formed with a plurality of central terminals and the outer fixing element is formed with a plurality of outer terminals. In addition, lead wires are formed to interconnect each of the plurality of central terminals and each of the plu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/12H01L23/495H01L23/50H05K1/18
CPCH01L2924/0002H01L23/49572H01L24/01H01L2924/01322H01L2924/181H01L2924/00H01L23/50
Inventor 池田博伸
Owner NEC CORP
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