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Memory devices and methods which may facilitate tensor memory access

A memory, memory address technology, used in memory systems, instrumentation, climate sustainability, etc.

Pending Publication Date: 2021-03-09
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This repetition, combined with processing speed, may require repeated memory accesses to perform tensor processing operations

Method used

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  • Memory devices and methods which may facilitate tensor memory access
  • Memory devices and methods which may facilitate tensor memory access
  • Memory devices and methods which may facilitate tensor memory access

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Embodiment Construction

[0035] This article describes methods, devices, and systems for tensor memory access. Many data in different physical addresses between the memory can be simultaneously read or written, for example, by various processing modes calculated by a tensor or matrix correlation. A memory controller that can include a data address generator can be configured to generate a memory address sequence for a memory access operation based on a dimension of the start address and tensive or matrix. At least one dimension of the tensor or matrix can correspond to rows, columns, diagonal, row, or nth dimension of the tensive or matrix. The memory controller can also include a buffer configured to read and write data from an address memory sequence or data generated according to an address memory sequence.

[0036] In general, memory components such as memory storage devices or flash memory perform read commands and write commands, the read commands and write commands receive and / or directly from th...

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Abstract

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employingvarious processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Description

[0001] Cross-reference [0002] The present application claims the application interests of the US Non-Primary Application No. 16 / 043, 921 submitted in July 24, 2018. The present application is combined herein by reference to all purposes. Background technique [0003] High-speed memory access and reduced power consumption is the features required for semiconductor devices. In recent years, systems that use multi-core processors to perform applications have led to faster access modes for storage devices (eg, dynamic random access memory (DRAM)) used as main memory, and more random access modes. For example, a typical access mode of DRAM is repeatedly reused in sequentially, read access, or write access, and a memory precharge. The storage device needs to be accessed more quickly. The efficiency and performance of the computing device may be affected by different storage devices. Therefore, there is a need for fast and efficient access mode. [0004] Tensor is usually associated w...

Claims

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Application Information

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IPC IPC(8): G06F12/10G06F12/02
CPCG06F12/0207G06F2212/1016G06F13/1673G06F13/1642G06F12/0223G06F12/10G06F12/0893G06F12/0864G06F12/0292G06F2212/253G06F2212/206G06F12/06G06F2212/173
Inventor 罗法隆J·卡明斯T·施米茨J·赫里茨
Owner MICRON TECH INC