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FPGA acceleration system and method, electronic equipment and computer readable storage medium

A technology for accelerating systems and electronic equipment, applied in the computer field, and can solve the problems of inflexible function realization and low system performance.

Pending Publication Date: 2021-03-16
ALIBABA GRP HLDG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present invention provide an FPGA acceleration system and method, electronic equipment, and a computer-readable storage medium to solve the defects of inflexible function implementation and low system performance in the prior art

Method used

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  • FPGA acceleration system and method, electronic equipment and computer readable storage medium
  • FPGA acceleration system and method, electronic equipment and computer readable storage medium
  • FPGA acceleration system and method, electronic equipment and computer readable storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] figure 1 A system block diagram of one embodiment of an FPGA acceleration system provided by the present invention. Such as figure 1 As shown, in the FPGA acceleration system provided by the embodiment of the present invention, the internal portion of the FPGA is provided with a control module 11 and a plurality of execution modules 13 for performing different operations.

[0035] The control module 11 is configured to analyze, generate scheduling information, wherein the scheduling information is included in the scheduling information of the execution module and the operation order of the execution module; execution module 13 for the control module. 11 Generated scheduling information execution operation.

[0036] In the embodiment of the present invention, when the FPGA is used for the database accelerated scene, the FPGA can be set on the computing node in the database, and the control module 11 is disposed inside the FPGA, for example, the microprocessor can be set i...

Embodiment 2

[0039] figure 2 A system block diagram of another embodiment of the FPGA acceleration system provided by the present invention. Such as figure 2 As shown in the above figure 1 Based on the embodiment, the storage module 12 can also be used to store intermediate data generated by execution module 13 execution operation.

[0040] In the embodiment of the present invention, in the host (Host), the CPU is connected to the memory and a memory (Storage). The interface of the FPGA is connected to the CPU through the PCIe bus. In the FPGA, each execution module 13 performs an operation according to the scheduling information under the control of the control module 11, the intermediate data generated during the execution process (ie, the input, output data of each execution module) can be stored in the storage of the FPGA inside. Module 12 to reduce the data interaction of the FPGA at the CPU, reduce the participation of the CPU, and improve the system new energy.

[0041] Specifically...

Embodiment 3

[0048] image 3 A system block diagram of a specific embodiment of the FPGA acceleration system provided by the present invention. Such as image 3 As shown, in the embodiment of the present invention, the FPGA connects the host (Host) through the PCIe bus. Based on the improvement of the FPGA and the development of the chip process, the current FPGA has the ability to complete the processing of complex SQL instructions independently, and therefore, multiple IP cores can be set in the FPGA, such as compression, decompression, filtering (Filter), polymerization (AGGR) ), Hash, sort, group binding (JOIN), projection (Proj), etc., and set a microprocessor capable of controlling and scheduling each execution module.

[0049] When the host generates control information, the control information is sent to the microprocessor in the FPGA via PCIe, and the microprocessor analyzes the control information to generate scheduling information for scheduling each execution module. Specifically,...

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PUM

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Abstract

The embodiment of the invention provides an FPGA acceleration system and method, electronic equipment and a computer readable storage medium. According to the system, a control module and a pluralityof execution modules used for executing different operations are arranged in an FPGA, the control module is used for analyzing received instructions and generating scheduling information, and the scheduling information comprises the execution modules needing to be scheduled for executing the instructions and the operation sequence of the execution modules; and the execution module is used for executing operation according to the scheduling information generated by the control module. According to the embodiment of the invention, the received instruction is analyzed to control and schedule eachexecution module in the FPGA to execute the operation so as to flexibly realize acceleration.

Description

Technical field [0001] The present invention relates to the field of computer technology, and more particularly to an FPGA acceleration system and method, an electronic device, and a computer readable storage medium. Background technique [0002] The field programmable gate array (hereinafter referred to as: FPGA) As a programmable logic device, since it can be reprogrammed according to different needs after manufacture, it can be configured to be configured to be configured. In the prior art, this characteristics of FPGA can be performed by each IP core (ie, execution module) to perform an acceleration of the database. [0003] When using FPGAs to accelerate, you can provide acceleration such as compression, decompression, filtering, projection, hash, etc., such as compression, decompression, filtering, projection, hash, and so on. [0004] In the process of implementing the present invention, it is found that the prior art has at least the problem: in the prior art, for differe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25257
Inventor 李峰
Owner ALIBABA GRP HLDG LTD