A CMOS reference voltage buffer with low output resistance

Abstract

The invention discloses a CMOS reference voltage buffer with low output resistance. The CMOS reference voltage buffer with low output resistance includes a single-pole high-gain OTA, a power transmission PMOS transistor Tp, a first feedback resistor R1 and a second feedback Resistor R2, the single-pole high-gain OTA includes a voltage source VDD, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4 , the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9 and the tenth NMOS transistor N10. The reference voltage buffer provided by the present invention has a very low output impedance at a low frequency, and the extra circuit overhead is small, which is beneficial to maintain low power consumption.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a CMOS reference voltage buffer with low output resistance. Background technique [0002] see figure 1 As shown, it is the basic structure of the reference voltage buffer (the filter capacitor is not shown), and its output resistance can be expressed as: [0003] [0004] where A V，OTA is the DC voltage gain of an operational transconductance amplifier (OTA), g mP Indicates the transconductance of the PMOS transistor Tp. [0005] The power consumption constraint basically determines the R 1 , R 2 and g mP The value of , so the open-loop DC voltage gain of the OTA determines the size of the output resistance. The higher the open-loop DC voltage gain of the OTA, the lower the output resistance can be achieved. In addition, in order to ensure stability, the OTA here must also be unipolar. Therefore, the cascode structure is the basic structure choice for OTA. If...

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Problems solved by technology

However, it has two disadvantages: (1) the maximum value of the input reference voltage is limited, and the reference voltage generated by the general reference circuit is about 1.25V; (2) the common gate stage N 3 -N 4 The bias voltage V B2 An additional bias circuit is required to meet the requirements of the operating point; (3) There is also a problem of tight voltage space in a typical analog process (180nm CMOS process), resulting in a smaller actual equivalent transconductance and output resistance, so Difficult to achieve high voltage gain

[0015] Introducing negative feedback at the common gate level to enhance the equivalent transconductance of the common gate tube is a way to increase the voltage gain, but this method requires four additional branch currents, usually used for high-speed full differential with looser power consumption constraints In the structure, such as the fully differential OTA in the pipelined high-speed ADC

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