47results about How to "Small output resistance" patented technology

The invention discloses a micro-grid multi-inverter parallel voltage control method for droop control of robust power. The method comprises the following steps of: specific to each inverter in a micro-grid, computing and synthesizing an inverter output reference voltage by adopting a robust power droop controller; and introducing virtual complex impedance containing a resistance component and an inductive impedance component, and keeping inverter output impedance in a pure resistance state under a power frequency condition by adopting a multi-loop voltage control method based on virtual impedance and quasi-resonance PR (Proportional-Resonant) control, thereby realizing micro-grid multi-inverter parallel running and power equation, wherein the robustness of a micro-grid parallel system on numeric value computing errors, parameter drift, noise interference and the like is enhanced. Due to the adoption of the method, the defects of larger loop current of a parallel system, non-uniform power distribution and the like caused by the inductivity of the impedance output by inverters in the conventional droop method are overcome; and the method is suitable for multi-grid parallel uniform current control in a low-voltage micro-grid.

The invention discloses a charging circuit and a charger using the charging circuit, comprising a generator; a voltage reducing circuit, a current controller, a mode selector, and a monitor. The invention is characterized in that the voltage reducing circuit reduces the output voltage of the generator to predetermined voltage; the current controller controls the charging current supplied to a secondary battery by the voltage reducing circuit according to the electric quantity produced by the generator; the mode selector selects charging mode; the monitor monitoring the stored electric quantity; in the process of charging, the voltage reducing circuit receives the output of the generator by high voltage and small current, and charges the secondary battery by low voltage and high current.

The invention discloses a fast transient response CMOS low-dropout linear voltage regulator. The inverting input terminal of the error amplification circuit is connected to the reference voltage Vref, and the non-inverting input terminal of the error amplification circuit is connected to the sampling output terminal Vf of the sampling resistance circuit. The output terminal of the error amplifier circuit is connected to the gate of the power tube through the slew rate enhancement circuit; the positive power terminal of the error amplifier circuit, the positive power terminal of the slew rate enhancement circuit and the source of the power tube are connected to form the input of the regulator body terminal Vin; the drain of the power tube is connected to the positive power supply terminal of the sampling resistor to form the output terminal Vout of the voltage regulator body; the negative power supply terminal of the error amplifier circuit, the negative power supply terminal of the slew rate enhancement circuit and the negative power supply terminal of the sampling resistor After the terminals are connected, the ground terminal GND of the voltage regulator body is formed. The invention has higher conversion rate and transient response.

The invention discloses an output buffer circuit which has noise resistant and load adaptive capacity. The buffer circuit comprises a pre-driver, a first charge and discharge circuit and a second charge and discharge circuit. The pre-driver provides the first charge and discharge circuit and the second charge and discharge circuit with a drive signal so as to enable the first charge and dischargecircuit and the second charge and discharge circuit to be electrified at different times; the PMOS tube which is connected in a diode manner and the NMOS tube which is connected with a diode in the first discharge circuit cut off automatically when the charge and discharge is almost over, thereby enhancing a resistance which can be seen from an output end and ensuring the circuit has excellent noise resistant property. Additionally, the structure of the invention can lead the electrification time of two discharge circuits to take up the proportion size of the overall switching process, that is, the driving capacity provided by the circuits changes along with the change of a load, so that load adaptive capacity is possessed. Therefore, the invention has the advantages of low consumption, noise resistance, and load adaptive property.

The present invention discloses an electrode falling detection circuit. The electrode falling detection circuit comprises an impedance detection unit and a processor; the impedance detection unit is connected with electrodes and used for receiving impedance detection signals, also uses the impedance detection signals to detect electrode-loaded impedance and generates impedance signals; and the processor is connected with the impedance detection unit and used for providing the impedance detection signals for the impedance detection unit, calculates an impedance value according to the impedancesignals generated by the impedance detection unit and judges whether the electrodes fall off from a human body or not according to the impedance value. By detecting the electrode-loaded impedance value, if the impedance value is larger than a threshold value, the electrodes are considered to fall off from the human body and detection of falling-off of the electrodes from the human body is achieved.

The invention discloses a CMOS reference voltage buffer with low output resistance. The CMOS reference voltage buffer with low output resistance includes a single-pole high-gain OTA, a power transmission PMOS transistor Tp, a first feedback resistor R1 and a second feedback Resistor R2, the single-pole high-gain OTA includes a voltage source VDD, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4 , the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9 and the tenth NMOS transistor N10. The reference voltage buffer provided by the present invention has a very low output impedance at a low frequency, and the extra circuit overhead is small, which is beneficial to maintain low power consumption.