Output buffer circuit

Abstract

The invention discloses an output buffer circuit which has noise resistant and load adaptive capacity. The buffer circuit comprises a pre-driver, a first charge and discharge circuit and a second charge and discharge circuit. The pre-driver provides the first charge and discharge circuit and the second charge and discharge circuit with a drive signal so as to enable the first charge and dischargecircuit and the second charge and discharge circuit to be electrified at different times; the PMOS tube which is connected in a diode manner and the NMOS tube which is connected with a diode in the first discharge circuit cut off automatically when the charge and discharge is almost over, thereby enhancing a resistance which can be seen from an output end and ensuring the circuit has excellent noise resistant property. Additionally, the structure of the invention can lead the electrification time of two discharge circuits to take up the proportion size of the overall switching process, that is, the driving capacity provided by the circuits changes along with the change of a load, so that load adaptive capacity is possessed. Therefore, the invention has the advantages of low consumption, noise resistance, and load adaptive property.

Description

technical field [0001] The invention belongs to the field of microelectronic integrated circuits, and in particular relates to a low-noise, load-adaptive high-speed output buffer circuit, which is especially suitable for occasions where the output load of a chip changes and the noise performance is high. Background technique [0002] The output buffer circuit provides connections between the internal circuit of the chip and the external circuit. It is used in occasions where the core voltage of the chip is different from the external voltage of the chip. The high-speed output buffer circuit can provide voltage conversion, increase the driving capability of the circuit, and reduce output ringing. , these functions make the output buffer circuit widely used in the output of digital chips and the interface of digital and analog circuits. In the design of the output buffer circuit, the main concerns of the predecessors include: driving capability, low power consumption, slew rat...

AI Technical Summary

Problems solved by technology

In the design of the output buffer circuit, the main concerns of the predecessors include: drive capability, low power consumption, slew rate and other performance, less involving noise resistance and load adaptation

Through theoretical calculation and simulation analysis, it can be seen that under certain conditions of capacitance C and inductance L, the smaller the output resistance R of the RLC circuit shown in Figure 1(b), the faster the switching speed of the circuit, but at this time the noise of the circuit is also higher. In addition, the larger the output resistance, the smaller the noise of the circuit, but the switching speed of the circuit becomes slower

Images