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Buffer circuit used for LDO

A buffer circuit, input voltage technology, applied in the direction of adjusting electrical variables, control/regulating systems, instruments, etc., can solve the problems of large power consumption, large circuit area, complex circuit structure of buffer amplifiers, etc. consumption reduction effect

Inactive Publication Date: 2017-08-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that the power consumption of the buffer amplifier of the existing LDO is too large, or the circuit structure is too complicated to cause the circuit area to be too large

Method used

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  • Buffer circuit used for LDO
  • Buffer circuit used for LDO

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Embodiment Construction

[0010] The present invention is described in detail below in conjunction with accompanying drawing

[0011] figure 1 It is the overall circuit block diagram of LDO, which contains the buffer circuit of the present invention. As shown in the figure, the LDO overall circuit includes a reference, an error amplifier, a buffer circuit, an adjustment tube, a feedback loop, and some protection circuits (not shown in the figure). The basic working principle of the entire LDO is to sample the output voltage value through the feedback resistors R1 and R2, and feed back to the error amplifier to compare with the reference voltage. Then the error signal is amplified to drive the adjustment tube to change its resistance to keep the output voltage stable. Compared with the traditional LDO without a buffer circuit, the slew rate of the error amplifier is limited due to the limitation of circuit power consumption. Therefore, when the output fluctuates sharply, the output of the error ampli...

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Abstract

The invention belongs to the technical field of integrated circuits, and relates to a buffer circuit used for an LDO. Compared with a traditional LDO circuit, in the buffer circuit used for the LDO, the buffer circuit is added; the buffer circuit can improve the driving capacity of an error amplifier, so that the transient response of the LDO is drastically improved; besides, since the buffer circuit is composed of a source follower, the source follower has an extremely low output resistance, and therefore, a pole P3 generated by an output end of the error amplifier can be pushed to a higher frequency, so that the stability of the circuit is not influenced by the pole P3; more importantly, in the buffer circuit, through the design of the circuit structure, the quiescent current of the buffer is reduced, which has very significant importance in the reduction of the overall power consumption of the LDO circuit.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to a buffer circuit for LDO. Background technique [0002] In the LDO integrated circuit chip, the adjustment tube in the circuit is required to pass a large current, so its size is generally large. As a result, the input capacitance of the adjustment tube is relatively large. In the LDO feedback loop, the output voltage feedback signal is input to the error amplifier and then drives the pass transistor. The error amplifier has limited drive current due to power dissipation constraints. This condition can lead to poor transient response of the circuit. In addition, the error amplifier output pole is small due to the large output capacitance and large output resistance of the error amplifier. This pole is generally the third pole P3 which will degrade the stability of the circuit. The current solution is generally to add a buffer amplifier at the output end of the error...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 方健王科竣冯磊陈智昕刘振国张波杨健
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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