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Semiconductor memory device and method of manufacturing the same

A technology for storage devices and semiconductors, applied in semiconductor devices, read-only memories, static memories, etc., can solve problems such as limitations and achieve the effect of improving reliability

Pending Publication Date: 2021-03-23
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because the equipment used to form fine patterns can be expensive, the integration density of 2D semiconductor devices continues to increase, but will be limited

Method used

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  • Semiconductor memory device and method of manufacturing the same
  • Semiconductor memory device and method of manufacturing the same
  • Semiconductor memory device and method of manufacturing the same

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0025] figure 1 is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept.

[0026] refer to figure 1 , according to some embodiments, a semiconductor memory device may include a common source line CSL, a plurality of bit lines BL0 to BL2 , and a plurality of cell strings CSTR provided between the common source line CSL and the bit lines BL0 to BL2 .

[0027] The common source line CSL may be a conductive layer disposed on the semiconductor substrate or a dopant region formed in the semiconductor substrate. The bit lines BL0 to BL2 may be conductive patterns (eg, metal lines) spaced vertically (ie, in the Z direction) from the semiconductor substrate. The bit lines BL0 to BL2 may be two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 to BL2 . Accordingly, the cell strings CSTR may be two-dimensionally arranged on the c...

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PUM

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Abstract

Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked ona substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer.The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulatinglayers.

Description

technical field [0001] Embodiments of the inventive concepts relate to semiconductor memory devices, and more particularly, to three-dimensional (3D) nonvolatile memory devices and methods of manufacturing the 3D nonvolatile memory devices. Background technique [0002] Semiconductor devices have been highly integrated to provide improved performance and generally lower manufacturing costs. The integration density of a semiconductor device can directly affect the cost of the semiconductor device, resulting in a generally high demand for highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be determined by the area of ​​a memory cell unit. Therefore, the integration density of typical 2D or planar semiconductor devices can be affected by the techniques used to form fine patterns. However, because the equipment for forming fine patterns can be expensive, the integration density of 2D semiconduct...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11582H01L27/11565
CPCH10B43/10H10B43/27G11C16/0483H10B41/50H10B41/27H10B43/50H01L29/792H01L29/66833H10B69/00H10B43/35G11C5/025
Inventor 丁相勋洪祥准沈善一金坰显文彰燮
Owner SAMSUNG ELECTRONICS CO LTD