AXI bus structure and chip system

Abstract

The invention provides an AXI bus structure and a chip system. The AXI bus structure comprises: at least two main function unit groups, wherein each main function unit group comprises at least two main function units; at least two first routing units, wherein the at least two first routing units and the at least two main function unit groups are in one-to-one correspondence with the at least two first routing units, and each first routing unit is connected with each main function unit of the corresponding main function unit group through an AXI bus; at least two second routing units, wherein each second routing unit is connected with each first routing unit through an AXI bus; and at least two slave function unit groups, wherein each slave function unit group comprises at least two secondslave function units, the at least two slave function unit groups are in one-to-one correspondence with the at least two second routing units, and each second routing unit is connected with each slavefunction unit corresponding to the slave function unit group through an AXI bus.

Description

technical field [0001] The present application relates to the technical field of chip technology, and in particular to an AXI bus structure and a chip system. Background technique [0002] The on-chip interconnection bus (Network On Chip) refers to the connection relationship between various systems or modules in the chip, and is mainly used to realize data exchange between subsystems or functional modules in the chip. In AI processing chips, the huge data throughput requirements have brought many challenges to the design of the on-chip interconnection bus. For example, in a multi-core NPU (Neural network Processing Unit, neural network processor), the bandwidth requirements for data interaction between multiple cores and data interaction with OCM (On chip memory, on-chip storage) are huge. In order to support high bandwidth, high clock frequency and wide bus bits have become the basic characteristics of AI processor on-chip interconnection bus. At the same time, multi-cor...

AI Technical Summary

Problems solved by technology

At the same time, multi-core also makes the number of interconnection bus lines become huge, which brings serious congestion (congestion) problems to the chip back-end implementation.

Images