Dynamic caching method for solving storage bandwidth efficiency of universal AI processor

Abstract

The invention relates to a dynamic caching method for solving the storage bandwidth efficiency of a unisersal AI processor, which comprises adding a bit flag bit C in a caching line, continuously storing a data segment in conventional caching line data, and reading the data according to the following steps: S1, judging according to a CPU (Central Processing Unit) reading instruction, and if the data segment is read, entering S2; s2, determining the position of the data segment according to the index domain; s3, comparing the tag of the data segment with the tag in the cache, and if the tag of the data segment is consistent with the tag in the cache, entering S4; s4, checking a V bit, and if the V bit is 1, entering S5; s5, checking the C bit, and if the C bit is 1, entering S6; s6, according to the length of the data needing to be read by the reading instruction, checking the C bits in the cache behind the initial address, if the C bits of the continuously stored data are all set to be 1 and the data length meets the data reading length, performing continuous reading, and otherwise, performing cache miss. And the operation requirements of the CPU and the AI processor can be met at the same time.

Description

technical field [0001] The invention relates to a data cache, in particular to a dynamic cache method for solving storage bandwidth efficiency of a general AI processor. Background technique [0002] At present, artificial intelligence is widely used in various fields. Deep neural network technology has become a representative algorithm in the field of artificial intelligence. Key technologies such as character recognition, image classification, or speech recognition based on deep neural network technology have been widely used in search engines and intelligence. products such as mobile phones. [0003] The core computing unit of deep neural network technology is multiply-accumulate operation. Multiply-accumulator array is often used in matrix multiplication operation. Therefore, MAC (multiply-accumulator) array is the core of AI calculation. More and more general-purpose computing chips cater to AI For computing needs, a MAC array is specially added to improve computing po...

AI Technical Summary

Problems solved by technology

[0031] In view of the high-bandwidth data flow requirements of general-purpose AI processors, existing data caches need to transmit data in the basic unit of cache lines, and the data exchanged each time is the size of a single cache line, which obviously cannot meet the needs of new general-purpose AI processing. device needs

Images