Seal ring structure and preparation method thereof

A sealing ring and enhanced technology, which is applied in the field of sealing ring structure and its preparation, can solve the problems of unfavorable device miniaturization, occupation of integrated circuit chip area, and increase of chip area, and achieve the effect of avoiding stress or impurity damage
CN112701116BActive Publication Date: 2022-05-10HUNAN SANAN SEMICON CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HUNAN SANAN SEMICON CO LTD
Publication Date
2022-05-10

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A sealing ring structure and a preparation method thereof relate to the technical field of integrated circuits. The sealing ring structure includes an enhanced high electron mobility transistor, a diode group and a resistor manufactured through a semiconductor epitaxial layer. On the periphery of the device area; the anode of the diode group is used for metal connection with the first electrode of the semiconductor device, the cathode is metal connected with the first metal end of the resistor, and the second metal end of the resistor is used for metal connection with the second electrode of the semiconductor device; The gate of the type high electron mobility transistor is connected with the cathode metal of the diode group, the drain is used for connecting with the first electrode metal, and the source is used for connecting with the second electrode metal of the semiconductor device. The sealing ring structure can utilize the area of ​​the sealing ring to realize the electrostatic protection function, thereby saving the area of ​​the device.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the technical field of integrated circuits, in particular, it is applied to semiconductor devices, and relates to a sealing ring structure and a preparation method thereof. Background technique

[0002] Electro-Static discharge (ESD) is the phenomenon of charge release and transfer between integrated circuit chips and external objects. Due to the release of a large amount of charge in a short period of time, the energy generated by ESD is much higher than the capacity of the chip, so it is likely to cause temporary failure or even permanent damage to the function of the chip. Therefore, in order to avoid damage to integrated circuits by static electricity as much as possible, electrostatic discharge protection design is very important in improving product reliability and yield.

[0003] Generally, an integrated circuit is separately provided with an electrostatic protection structure, so as to protect the integrated circuit wh...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More