Phase-locked loop control method based on linear active disturbance rejection technology
A technology of active disturbance rejection control and control method, applied in the field of phase-locked loop, can solve the problems of strong coupling, difficult to obtain ideal control effect, strong nonlinear system parameter jump, etc.
Active Publication Date: 2021-04-23
TIANJIN UNIV +2
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The reason is that the PI control in the traditional phase-locked loop has many variables, strong coupling, or strong nonlinearity, severe unknown disturbances, and system parameter jumps, and it is difficult to achieve ideal control effects.
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[0031] The technical solutions in the embodiments of the present invention are clearly and completely described below in combination with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
[0032] The structural unit of the inverter unit is as figure 1 As shown, it consists of DC power supply, inverter bridge, LC filter, voltage, current sampling, two-phase stationary / two-phase rotating coordinate transformation (αβ / dq), phase-locked loop, constant power control strategy (PQ control) and PWM modulation link composition. Wherein, the phase-locked loop is the part represented by the LADRC-PLL of the present invention, and in the traditi...
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The invention provides a phase-locked loop control method based on a second-order linear active disturbance rejection technology, and the method comprises the steps: enabling the second-order linear active disturbance rejection control to serve as a controller of a phase-locked loop, and redesigning the system gain of the second-order linear active disturbance rejection control, so as to obtain an active-disturbance-rejection phase-locked loop algorithm capable of outputting stable frequency capability under the new system gain when the voltage is unbalanced and fluctuates; redesigning the system gain b0 of the second-order linear active disturbance rejection control to obtain a new system gain b0'; in other words, the value of the system gain b0 of the auto-disturbance rejection phase-locked loop is correspondingly changed according to the calculated grid-side voltage imbalance fluctuation degree, so that the fluctuation component in the output of the auto-disturbance rejection phase-locked loop at the moment is suppressed.
Description
technical field [0001] The invention relates to the relevant technical field of grid voltage behavior signal detection and grid load harmonic current extraction, in particular to a phase-locked loop suitable for grid voltage unbalanced state. Background technique [0002] The traditional Synchronous Reference Frame PLL (SRF-PLL) based on the synchronous rotating coordinate system can obtain phase information well when the three-phase voltage is balanced, but when the grid voltage drops, its output amplitude, frequency and There are fluctuations and errors in the phase information. The reason is that the PI control in the traditional phase-locked loop has many variables, strong coupling, or strong nonlinearity, severe unknown disturbances, and system parameter jumps, and it is difficult to achieve ideal control effects. Therefore, it is more necessary and urgent to find a new alternative structure with higher performance. Contents of the invention [0003] The purpose of ...
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Login to View More IPC IPC(8): H03L7/24
CPCH03L7/24
Inventor 李永丽张威陈晓龙耿少博何亚坤常风然任江波蒋帅李仲青窦雪薇
Owner TIANJIN UNIV