Multi-bare-chip package structure, chip and method

Abstract

The invention discloses a multi-bare-chip packaging structure, a chip and a method. The multi-bare-chip packaging structure comprises: an embedded bare chip which is buried in a substrate; a flip bare chip which is placed above the substrate and is electrically connected with the substrate through a conductor; and a bonding bare chip which is bonded above the flip bare chip and is electrically connected with the substrate through a bonding wire. According to the multi-bare-chip packaging structure, the cost is reduced, and the performance is improved.

Description

technical field [0001] The present invention relates to a semiconductor package, and more specifically, the present invention relates to a multi-die package structure, chip and method. Background technique [0002] The requirements of client electronics have increased significantly in recent years. Miniaturization and portability are unstoppable trends, driving more compact chip packages. Correspondingly, while portable electronic devices have more functions and better performance, their volumes are becoming smaller and smaller. Therefore, today's power supply systems are required to have smaller size, higher power output, more functions and higher efficiency. Under these requirements, some technologies integrate switching devices such as field effect transistors and controllers into a single die. However, generally speaking, the controller uses a complementary metal-oxide-semiconductor process (CMOS process), which requires 18 to 20 mask manufacturing processes; while th...

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Problems solved by technology

Therefore, this single die is expensive to manufacture due to the fact that the switching device and the controller are manufactured together.

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