Chip interconnection system based on AXI

A technology for interconnecting systems and chips, applied in instruments, electrical digital data processing, etc., can solve problems such as performance discounts, large IO consumption, and extremely high timing requirements for parallel interfaces

Pending Publication Date: 2021-04-30
S2C
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] AXI is an on-chip bus for high performance, high bandwidth, and low latency. However, in the field of prototype verification, user designs will be divided, and a

Method used

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  • Chip interconnection system based on AXI
  • Chip interconnection system based on AXI
  • Chip interconnection system based on AXI

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Embodiment Construction

[0027] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0028] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, a...

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Abstract

The invention provides a chip interconnection system based on AXI, and the system comprises physical layer connection: carrying out inter-chip physical layer communication by adopting a high-speed serial bus; data link layer communication, wherein a data link layer comprises a CRC unit which is used for ensuring the integrity of data transmission; a link detection unit which is used for detecting the stability of a link layer; and protocol layer communication, wherein the protocol layer provides an AXI interface and an AXI LITE interface for users on the upper layer. According to the invention, AXI bus interconnection between chips is realized through the high-speed serial bus, the highest bandwidth is realized with the least IO number, and the reliability of data transmission is ensured.

Description

technical field [0001] The present disclosure relates to the technical field of electronic computer software, in particular to an AXI-based chip interconnection system. Background technique [0002] AXI is an on-chip bus for high performance, high bandwidth, and low latency. However, in the field of prototype verification, user designs will be divided, and a large amount of IO will be consumed between modules. The parallel interface has extremely high timing requirements. The performance achieved will be greatly compromised. Contents of the invention [0003] In view of this, an embodiment of the present disclosure provides an AXI-based chip interconnection system, which implements the AXI bus interconnection between chips through a high-speed serial bus, achieves the highest bandwidth with the least number of IOs, and ensures the reliability of data transmission. [0004] In order to achieve the above object, the present invention provides the following technical solutio...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4068G06F13/4221G06F13/4282G06F2213/0002G06F2213/0004G06F2213/3852
Inventor 周超谢超
Owner S2C
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