Etching method
A polysilicon layer and substrate technology, applied in electrical components, circuits, semiconductor/solid-state device manufacturing, etc., can solve the problems of device stability and poor yield, and achieve the effect of improving stability and manufacturing yield
Active Publication Date: 2022-06-07
HUA HONG SEMICON WUXI LTD
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Problems solved by technology
[0004] The present application provides an etching method, and the manufacturing process of power devices using this etching method can solve the problem of poor device stability and yield due to cracks in the manufacturing process of power devices provided in the related art
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[0026] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.
[0027] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...
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The present application discloses an etching method, including: providing a substrate, including at least one unit region on the substrate, two trenches are formed in each unit region, and the gap between the two trenches in each unit region is A gate oxide is formed on the substrate; a polysilicon layer is formed on the substrate, and the polysilicon layer fills the trench to form a DTI structure; the target area of the polysilicon layer is covered with photoresist through a photolithography process; etching is performed in an ICP device to remove For the polysilicon layer in areas other than the target area, during the etching process, by adjusting the etching parameters, the etched morphology of the junction between the polysilicon layer and the DTI structures on both sides is arc-shaped and has no acute angle; resistance. In the present application, during the process of etching the polysilicon layer connected to the DTI structure, by adjusting the etching parameters, the etching morphology of the connection between the polysilicon layer and the DTI structure on both sides is arc-shaped and has no acute angle, thereby improving Improve device stability and manufacturing yield.
Description
technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to an etching method applied in the manufacturing process of power devices. Background technique [0002] refer to figure 1 , which shows a cross-sectional view of a power device provided in the related art. like figure 1 As shown, a deep trench isolation (deep trench isolation, DTI) structure 120 is formed in the substrate 110, a gate oxide 130 is formed between the DTI structures 120 on the substrate 110, a polysilicon layer 140 is formed on the gate oxide 130, and the polysilicon layer 140 connects the DTI structures 120 together, and an interlayer dielectric (inter layer dielectric, ILD) layer 150 is formed on the polysilicon layer 140 . [0003] like figure 1 As shown, in the power device provided in the related art, the connection between the polysilicon layer 140 and the DTI structure 120 (such as figure 1 The angle of the chamfer α formed b...
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IPC IPC(8): H01L21/762
CPCH01L21/76224H01L21/76208
Inventor 冯大贵吴长明欧少敏崔艳雷
Owner HUA HONG SEMICON WUXI LTD