Dual-depth via device and process for large back contact solar cells

Abstract

Dual-depth through-wafer-via semiconductor devices and methods for fabricating dual-depth through-wafer-via semiconductor devices are disclosed. In particular, back- contact-only multijunction photovoltaic cells and the process flows for making such cells are disclosed. The dual-depth through-wafer-via multijunction photovoltaic cells include through-wafer-vias for interconnecting the front surface epitaxial layer to a contact pad on the back surface. Before etching the through-wafer-vias the substrate is thinned to less than 150 pm. The dual-depth through-wafer-vias are formed using a two-step wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers. Low-stress passivation layers are used to reduce the thermo-mechanical stress of the semiconductor devices. A bypass diode is integrated in the recess on the backside formed by the dual-depth through-wafer structure.

Description

technical field [0001] The present disclosure relates to photovoltaic cells, methods for manufacturing photovoltaic cells, methods for assembling solar panels, and solar panels including photovoltaic cells. In particular, the present disclosure relates to multi-junction photovoltaic cells with through-wafer vias and discrete bypass diodes integrated onto the backside. The multi-junction photovoltaic cell includes dual-depth through-wafer vias for interconnecting the front surface epitaxial layers to contact pads on the back surface and for providing recesses on the backside to allow mounting of bypass diodes. The dual-depth through-wafer vias are formed using a two-step wet etch process that removes portions of the substrate and then non-selectively removes the semiconductor without significant differences in etch rates between heteroepitaxial III-V semiconductor layers Material. A low stress passivation layer is used to improve device reliability over a wide temperature ran...

AI Technical Summary

Problems solved by technology

Large area PCBs with sufficiently low CTE are either not available or expensive

Images