PMOS device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and provides a PMOS device and a preparation method of the PMOS device. The PMOS device comprises a substrate, a SiGe layer, a source region, a drain region, a grid electrode and a side wall spacer, wherein the SiGe layer is arranged on the substrate; the source region and the drain region are arranged in the SiGe layer at an interval; the grid electrode is arranged on the SiGe layer; and the sidewall spacer is disposed outside the gate. According to the PMOS device, the source region and the drain region are combined with the SiGe layer, and compatibility with HKMG integration is realized, so the PMOS device has the advantages of high hole mobility, high device working speed, good frequency characteristic and the like. The preparation method is high in integration level and low in manufacturing cost.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, and in particular to a PMOS device and a method for preparing the PMOS device. Background technique [0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. However, with the rapid development of microelectronics technology, the feature size of the device is continuously reduced, the circuit speed is continuously accelerated, static leakage, short channel effect, mobility degradation, power density increase and other physical limits make the performance of the device continue to deteriorate, and the integrated circuit gradually tends to Near its physical and process limits, traditional silicon-based devices an...

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Problems solved by technology

However, with the rapid development of microelectronics technology, the feature size of the device is continuously reduced, the circuit speed is continuously accelerated, static leakage, short channel effect, mobility degradation, power density increase and other physical limits make the performance of the device continue to deteriorate, and the integrated circuit gradually tends to Close to its physical and process limits, traditional silicon-based devices and processes gradually show their defects and deficiencies

[0003] The integrated circuit mainly adopts a complementary CMOS structure. The device that mainly affects the area and speed in this structure is PMOS, and the structure and manufacturing process of the PMOS device in the prior art cannot meet its highly integrated requirements, that is, its mobility. Lower, the speed of the integrated circuit is lower, and the circuit area is larger

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