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Extendible time-sharing bus structure

A bus structure and bus technology, applied in instruments, electrical digital data processing, etc., can solve the problems of increasing memory wiring and packaging costs, lack of scalability, and increasing system PCB costs.

Inactive Publication Date: 2003-11-19
SUNPLUS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] When the aforementioned micro-control system increases the memory capacity, the width of the address bus 51 must also increase accordingly, for example, when the memory capacity is increased to 4M bytes, it must be increased to 22 address lines at this time. In addition to the cost of the system PCB, it will also increase the cost of wiring and packaging of the memory, and the memory capacity of the entire system is not expandable after the design is completed, but has its production and use restrictions. Therefore, the aforementioned micro-control system It is necessary to improve the bus structure

Method used

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  • Extendible time-sharing bus structure

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Embodiment Construction

[0026] For a preferred embodiment of the time-sharing bus structure of the present invention, please refer to figure 1 As shown, it is used for reading and writing data between a microprocessor device 11 and at least one memory device 12. In this embodiment, the microprocessor device 11 is a microprocessor 111, and the memory device 12 is a memory 121 . This bus structure mainly comprises a microprocessor bus interface 13 and a memory bus interface 14, wherein, this microprocessor bus interface 13 is an N byte address and data shared bus 15 and at least two control lines 16 and the The memory bus interface 14 is connected. The address and data shared bus 15 is used to transmit address and data information between the microprocessor 111 and the memory 121, and the at least two control lines 16 are used to determine that the address and data shared bus 15 is used to transmit address, read data or write data.

[0027] The expandable real-time bus structure of the present embo...

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Abstract

The present invention relates to a structure capable of expanding time-shared bus, and is mainly characterized by that it utilizes the bus interface of microprocessor and memory and uses an address and data-shared bus to transfer the address and data to the between of microprocessor and memory in time-sharing mode, and ultizes the logic combination of two control lines to define that the said address-and data-shared bus is used for transferring address, reading data or writing data so as to reduce foot position for making interface and can obtain a storage space with elasticity and multiple.

Description

technical field [0001] The invention relates to a bus of a computer, in particular to a time-sharing bus structure with an expandable address space. Background technique [0002] The known micro-control system is mainly composed of microprocessor, memory and input and output devices, such as Figure 5 As shown, the transmission of data between the microprocessor 55 and the memory 54 (or I / O device) is carried out through a set of address bus 51, a set of data bus 52 and a set of read and write control signal lines 53, Wherein, the address bus 51 is used to carry the address of the memory 54 (or the I / O device), and the width of the address bus 51 represents the size of the memory space, for example, 16 address lines represent that the maximum memory capacity is 64k group of bytes (byte). [0003] When the aforementioned micro-control system increases the memory capacity, the width of the address bus 51 must also increase accordingly, for example, when the memory capacity is...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40
Inventor 李新洲龙章俊
Owner SUNPLUS TECH CO LTD