CP/FT test method, device and system, electronic equipment and medium

Abstract

The invention discloses a CP / FT test method, which comprises the following steps of: generating test excitation according to an SPI time sequence diagram; injecting the test excitation into the test chip through an SPI interface; acquiring an output value of the test chip under test excitation; and determining whether the test chip is qualified or not according to the output value. According to the method, the test time can be greatly saved, the test cost is reduced, and the defect that the test cost is relatively high due to low transmission frequency when a serial port protocol is adopted to carry out CP / FT test in the related technology is avoided. The invention also provides a CP / FT test device and system, electronic equipment and a computer readable storage medium, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the technical field of CP / FT testing, in particular to a CP / FT testing method, device, system, electronic equipment and computer-readable storage medium. Background technique [0002] During the chip manufacturing and packaging process, due to many factors, not every chip is a circuit with correct function. The CP test stage is to screen out bad chips as much as possible before chip packaging, reduce packaging costs, and select only those test items that have a greater impact on yield as much as possible. Test items that are difficult to test and costly but have a low fail rate. It can be tested in the FT stage. These items are of little significance in the CP stage and will only increase the cost of the test. In the FT stage, after the chip is packaged, the CP test is successful, but the items that have not been tested in the CP stage are tested. [0003] In related technologies, the chip FT test program is updated ...

AI Technical Summary

Problems solved by technology

The CP test stage is to screen out bad chips as much as possible before chip packaging, reduce packaging costs, and select only those test items that have a greater impact on yield as much as possible. Test items that are difficult to test and costly but have a low fail rate. It can be tested in the FT stage. These items are of little significance in the CP stage and will only increase the cost of the test; in the FT stage, after the chip is packaged, the CP test is successful, but the items that have not been tested in the CP stage are tested.

[0003] In related technologies, the chip FT test program is updated based on the serial port protocol. Since the fastest baud rate of the serial port protocol is 921600b / s, the transmission frequency is still KHz level, and the speed is very low. This has a great impact on the test cost, because CP The test of / FT is charged at the second level, the test time is long, and the test cost increases, resulting in an increase in the total production cost of the chip and a decrease in chip profit

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