PCIe device link training control method and system

Abstract

The invention discloses a PCIe device link training control method and system, and the method comprises the steps of: setting a power-on reset register of a PCIe device to be invalid, so as to release a PCIe power-on reset signal; respectively configuring a first register corresponding to a PCIe PHY, a second register corresponding to a PCIe controller and a third register corresponding to a PCIe application layer; polling and reading a value of an idle register of a receiving end to judge whether a host end starts link training, and if so, starting an enable signal of link training of the PCIe device through a fourth register, wherein the fourth register is a link training and state machine enabling register, and when the information that the link training is successful is received, interrupting the link training. Link training between a host end and the PCIe device can be automatically completed through the PCIe device, the requirement for the type of the host is lowered, and the compatibility of the PCIe device to different hosts is improved.

Description

technical field [0001] The invention relates to the field of PCIe equipment, in particular to a PCIe equipment link training control method and system. Background technique [0002] PCIe (Peripheral Component Interconnect Express, the latest bus and interface standard) is a high-speed serial computer expansion bus, with the characteristics of fast transmission speed, end-to-end reliable transmission, support for hot plugging, low power consumption management and quality of service , has been widely used in personal computers, servers, solid-state drives, data centers, network cards and other fields, and has helped the rapid development of this field. [0003] According to the PCIe protocol, the cold reset and warm reset of the PCIe reset types need to use the bypass signal to basically reset, the reset time is long, and link training needs to be performed again. According to the PCIe protocol, if the host side provides a basic reset signal, then the signal should meet the t...

AI Technical Summary

Problems solved by technology

According to the PCIe protocol, if the host side provides a basic reset signal, then the signal should meet the timing requirements specified in the PCIe protocol, but the protocol does not specify how to reset when the host side does not provide a basic reset signal. When the host side PCIe interface does not provide a basic reset PCIe device fails to complete link training and reset when signaling

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