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A Realization Method of Embedded Configurable Logic

A technology to achieve methods and goals, applied in the field of configurable logic, can solve problems such as high development cost, long development time, and difficult product differentiation

Active Publication Date: 2021-10-26
弘大芯源(深圳)半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] To sum up, today’s consumer market has a fast update speed, high chip integration density, long development time, high development cost, difficult product differentiation, and fierce product competition. Therefore, how to take into account short development time, low price, powerful functions and performance, and product differentiation. And coping with frequent new versions of specifications or protocols has become the most difficult problem in ASIC development and manufacturing

Method used

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  • A Realization Method of Embedded Configurable Logic
  • A Realization Method of Embedded Configurable Logic
  • A Realization Method of Embedded Configurable Logic

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0087] The present invention provides an implementation method of embedded configurable logic, such as Figure 4 shown, including:

[0088] Step 1: Determine the set of hardware design nodes and the set of software design nodes on the target integrated circuit;

[0089] Step 2: Obtain the target requirements of the user, and split the target requirements to obtain hardware requirements and software requirements;

[0090] Step 3: first matching the hardware requirement with the hardware design node set to obtain the hardware target node, and performing a second match between the software requirement and the software design node set to obtain the software target node;

[0091] Step 4: Configure hardware functions related to hardware requirements on the hardware target node, and at the same time, configure software functions related to software requirements on the software target node to execute corresponding functions.

[0092] Specific examples for the above steps 1-4 are as ...

Embodiment 2

[0108] Based on Embodiment 1, in step 1, the hardware design node set includes:

[0109] Different hardware blocks on the target integrated circuit, and the hardware blocks are non-programmable functional blocks for performing a first function related to hardware requirements;

[0110] In step 1, the software design node set includes:

[0111] Different programmable logic blocks on the target integrated circuit can be electrically edited to perform secondary functions related to software requirements, or to automatically supplement or enhance tertiary functions that cannot be performed by existing hardware blocks.

[0112] The beneficial effects of the above technical solution are: by determining the set of hardware design nodes and the set of software design nodes, it is convenient to effectively execute corresponding functions, and it is also convenient to supplement or enhance other functions, and through the effective distinction of functions designed by software and hardw...

Embodiment 3

[0114] Based on Embodiment 2, the process of executing the second function related to the software requirement function includes:

[0115] determining programmable logic blocks on the target integrated circuit;

[0116] Provide users with a method for adding specific functions based on the programmable logic block, call specific instructions related to the software requirements from the method, and add specific functions according to the specific instructions;

[0117] At the same time, comparing the target integrated circuit with the added specific function and the integrated circuit to be compared is used to distinguish the products in the product lines of the respective integrated circuits, and at the same time, differentiate the functions of the products;

[0118] Wherein, the added specific function is the corresponding second function to be executed.

[0119] In this embodiment, the specific instruction is to call a corresponding method to implement adding functions, wh...

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Abstract

The invention provides an implementation method of embedded configurable logic, comprising: step 1: determining the set of hardware design nodes and the set of software design nodes on the target integrated circuit; step 2: obtaining the target requirement of the user, and performing Split to obtain hardware requirements and software requirements; Step 3: First match the hardware requirements with the hardware design node set to obtain the hardware target node, and perform the second match between the software requirements and the software design node set to obtain the software target node; step 4: Configure the hardware functions related to the hardware requirements on the hardware target nodes, and at the same time, configure the software functions related to the software requirements on the software target nodes to execute the corresponding functions. By effectively distinguishing functions in hardware design and software design, the development cycle can be effectively reduced and product differentiation can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an implementation method of embedded configurable logic. Background technique [0002] Application-specific integrated circuits ("ASICs") or system-on-integrated chips ("SOCs") currently available in the market are designed to reach billions of transistors (hereinafter referred to as "ASICs"), which also include many qualitative functions Module (IntellectualProperties "IP"), for example, operation instruction center ("CPU", "ARM", "DSP", "MCU", etc.), system logic controller ("SLC"), external wired communication, wireless communication network system , graphics system, display control system, storage system, bus system ("BUS"), power supply system, digital / analog conversion system ("DAC / ADC"), multiple serial or parallel ports ("I / O") . [0003] Since ASICs provide a truly cost-effective way to implement large numbers of digital logic circuits to perform specific functi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445G06F13/42
CPCG06F9/44505G11C16/34
Inventor 张维忠洪学天黄宏嘉牛崇实林和
Owner 弘大芯源(深圳)半导体有限公司