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A single-bit multiplier

A multiplier and single-bit technology, applied in the field of single-bit multipliers, can solve the problems of large resources, large delay, occupation, etc., and achieve the effect of less resources and good signal-to-noise ratio

Active Publication Date: 2022-02-11
唐山恒鼎科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] First of all, decimation filtering will introduce delay, the greater the decimation rate, the greater the delay;
[0004] Secondly, converting to a multi-bit data signal will make subsequent signal processing operations (such as addition, subtraction, multiplication, etc.) complex in structure and take up relatively large resources;
[0005] In addition, data transmission is carried out through multiple data lines, which also consumes a lot of resources

Method used

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Embodiment Construction

[0049]The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0050] The purpose of the present invention is to provide a single-bit multiplier capable of directly performing multiplication of 1-bit data streams, with good signal-to-noise ratio and less resource occupation.

[0051] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

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Abstract

The invention relates to a single-bit multiplier. Both the multiplier and the multiplicand of the single-bit multiplier are 1-bit data streams, and the output is 1-bit data streams. The single-bit multiplier can complete the multiplication operation by using a configurable addition matrix module, a configurable multiply-add matrix module, and a configurable delay module, and has a better signal-to-noise ratio than multipliers in the prior art , and use fewer resources.

Description

technical field [0001] The invention relates to the field of electronic components, in particular to a single-bit multiplier. Background technique [0002] The delta-sigma analog-to-digital converter outputs a 1-bit data stream, which is usually decimated and filtered, converted into a multi-bit data signal, and then processed by a general digital signal processing method. Digital signal processing in this way has the following disadvantages: [0003] First of all, decimation filtering will introduce delay, the greater the decimation rate, the greater the delay; [0004] Secondly, converting to a multi-bit data signal will make subsequent signal processing operations (such as addition, subtraction, multiplication, etc.) complex in structure and take up relatively large resources; [0005] In addition, data transmission needs to be carried out through multi-bit data lines, which also consumes a lot of resources. [0006] Therefore, based on the above-mentioned shortcomings...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/52
CPCG06F7/52
Inventor 刘亚静袁书娟孙卫勇
Owner 唐山恒鼎科技有限公司