Neural network-oriented SIMT micro-architecture with variable calculation precision

Abstract

The invention relates to a neural network-oriented SIMT micro-architecture with variable calculation precision, which comprises an L1 instruction cache, an L0 instruction cache, a thread group scheduler, an instruction scheduling unit, a U-Core array, a special function unit, a register file and a read-write unit, and is characterized in that the L1 instruction cache, the L0 instruction cache and the thread group scheduler are sequentially connected with the instruction scheduling unit; the U-Core array and the special function unit are both connected with the instruction scheduling unit and the register file, the read-write unit is connected with the thread group scheduler, and the U-Core array is a computing unit array composed of a plurality of computing units U-Core which can be configured into different precisions. Compared with the prior art, the invention has the characteristics of high calculation flexibility, high calculation performance, high calculation efficiency, variable calculation precision, high universality and the like.

Description

technical field [0001] The invention relates to a SIMT microframework, in particular to a neural network-oriented SIMT microframework with variable calculation precision. Background technique [0002] Neural network (also known as artificial neural network) is a very widely used algorithm in the field of machine learning in recent years, and has achieved excellent results in computer vision, natural language processing and other fields, including convolutional neural network, loop neural network, etc. However, neural network algorithms often have a large amount of calculation, among which the largest amount of calculation is the convolutional neural network (Convolutional Neural Network, CNN). Typical convolutional neural networks include VGG, GoogLeNet, ResNet, etc. The amount of parameters Usually there are hundreds of MB, and the calculation amount can reach hundreds of MFLOPs (floating-point operations) or even GFLOPs, which puts higher demands on computing hardware. T...

AI Technical Summary

Problems solved by technology

[0013] Although Bit Fusion can use low-precision hardware in exchange for high throughput, Bit Fusion only supports fixed-point 2, 4, and 8 bits, thereby supporting the inference acceleration of neural networks, but the training of neural networks cannot support

In addition, the floating-point operations involved in scientific computing cannot be performed in Bit Fusion

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