Interface conversion circuit, multi-chip interconnection system and test method thereof

Abstract

The invention discloses an interface conversion circuit, a multi-chip interconnection system and a test method thereof. The interface conversion circuit is arranged in the chip and comprises a chip identification module, a data module, a control module, a write-in module, a read module and a comparison output module. The chip is located in the multi-chip interconnection system, and the chip contains a chip identification code. The chip identification module is used for identifying the chip identification code and outputting identification matching information; the data module is used for obtaining a test instruction and test data according to the test vector; the test instruction comprises an identification code instruction; the test data comprises write-in data and expected response data; the control module is used for judging whether the identification matching information is matched with the identification code instruction; the write-in module is used for outputting write-in data to the chip; the read module is used for collecting read data of the chip; and the comparison output module is used for obtaining and outputting an error signal according to the read data and the expected response data. According to the embodiment of the invention, the universality, flexibility and efficiency of chip testing can be improved.

Description

technical field [0001] The embodiment of the present invention relates to the technical field of chip testing, in particular to an interface conversion circuit, a multi-chip interconnection system and a testing method thereof. Background technique [0002] The traditional chip test is carried out through the Joint Test Action Group (JTAG) test pin. The test method of the standard JTAG protocol is to inject test vectors into the chip at the test data input port, and then obtain the test vector at the test data output port. The response signal of the chip is used to judge whether the function of the chip is normal. The test circuit inside the chip is responsible for receiving and executing the test vector sent by the external test system, and then feedback the result vector to the external chip test system. With the high development of computing requirements, the software has higher and higher requirements for computing power, resulting in larger and larger chips and more com...

AI Technical Summary

Problems solved by technology

With the high development of computing requirements, software has higher and higher requirements for computing power, resulting in larger and larger chip sizes and more complex test vectors, making the time required for chip testing longer and longer; and, as The subsequent constraints on chip yield and power consumption have made the application of technologies such as multi-chip interconnection and multi-card interconnection more and more popular. The chips in the interconnection system usually use high-speed ports to achieve interconnection; and most interconnection system-level The chip does not lead to the JTAG pin in the system board level application, which leads to the need for additional connection lines and configuration for chip testing

Therefore, the existing chip testing methods have the problems of poor versatility, poor flexibility, and low efficiency.

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