Apparatus for low energy accelerator processor architecture

Abstract

The invention relates to an apparatus for a low energy accelerator processor architecture. An example is arranged as an integrated circuit comprising a system bus having a data width N, wherein N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from memory; the low energy accelerator processor (745) configured to execute instruction words, coupled to the system bus and having a plurality of execution units including a load storage unit (771), a load coefficient unit (773), a multiplication unit (775), and a butterfly / adder ALU unit (779), each of the execution units configured to perform an operation in response to a retrieved instruction word (783); and a non-orthogonal data register file (759) including a set of data registers coupled to the plurality of execution units, the registers coupled to a selected one of the plurality of execution units. Additional methods and apparatus are also disclosed.

Description

[0001] Information about divisional applications [0002] This application is a divisional application of an invention patent application with an application date of April 1, 2016, an application number of "201610204401.8", and an invention title of "Device for Low Energy Accelerator Processor Architecture". [0003] Cross References to Related Applications [0004] This application is related to U.S. Patent Application No. 14 / 678,939 (Attorney Docket No. TI-75434), entitled "LOW ENERGYACCELERATOR PROCESSOR ARCHITECTURE WITH SHORT PARALLEL INSTRUCTION WORD," Said US patent application is filed concurrently with the present application and is hereby incorporated by reference in its entirety. technical field [0005] This application relates to microprocessors, such as those used in control systems and for processing data from sensors, and in particular to control applications where lower power consumption is particularly important, such as in portable battery-powered device...

AI Technical Summary

Problems solved by technology

While using these dedicated hardware accelerators will increase performance for each vector operation to be computed, this approach also tends to increase silicon area due to the addition of separate hardware functions for each type of vector computation to be accelerated

In addition, time-to-market and integrated circuit design process can be quite lengthy when using a dedicated hardware solution because of the need to change the dedicated hardware to address different applications

While computational performance will increase when using dedicated hardware blocks to perform certain vector calculations, the disadvantages of inflexibility and inability to modify the calculations outweigh the potential benefits

Furthermore, dedicated hardware accelerators are not used for operations other than the specific dedicated function being performed, so that integrated circuit designs with dedicated hardware accelerators can be an inefficient use of silicon area (depending on how often a specific function is performed)

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