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Device and method for reducing precision loss

A precision and addition operation technology, applied in the field of devices that reduce precision loss, to achieve the effect of reducing calculation errors

Pending Publication Date: 2021-06-25
LYNXI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, low-precision parameter calculation inevitably brings calculation errors

Method used

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  • Device and method for reducing precision loss
  • Device and method for reducing precision loss
  • Device and method for reducing precision loss

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0045] Example 1, such as Figure 5 As shown, a device for reducing precision loss of the present invention includes a module A and a module B. After module A executes a multiplication and addition operation task, it passes the multiplication and addition value to module B, module A is cleared, and module A continues to perform the next multiplication and addition operation task, and passes the multiplication and addition value to module B and the previous multiplication and addition value Accumulation is performed, module A is cleared, and after execution in sequence, multiple multiplication and addition operations are completed, and the accumulated value of module B is output.

[0046] In a possible implementation manner, the multiplication-accumulation value in module A is stored in register 1, and the accumulation value in module B is stored in register 2. Clock 1 counts the number of multiplication and addition operations of module A, and clock 2 counts the number of acc...

Embodiment 2

[0048] Example 2, such as Figure 6 As shown, a device for reducing precision loss in the present invention includes N modules A and one module B.

[0049] In a possible implementation manner, the multiplication and addition values ​​in the N modules A are respectively stored in a register i, where i represents a sequence number, and i=1, 2, . . . , N. For example, the multiply-accumulate value of the first module A is stored in register 1, the multiply-accumulate value of the second module A is stored in register 2, ..., the multiply-accumulate value of the Nth module A is stored in register N.

[0050] In a possible implementation manner, the clock i counts the times of multiplication and addition operations of the N modules A respectively, where i represents a serial number, and i=1, 2, . . . , N. For example, clock 1 counts the number of multiplication and addition operations of the first module A, clock 2 counts the number of times of multiplication and addition operatio...

Embodiment 3

[0053] Example 3, such as Figure 7 As shown, a device for reducing precision loss in the present invention includes N modules A and one module B. The difference from Embodiment 2 is that the device also includes: a register L, which is located before the selector MUX, and stores the multiplication and addition values ​​stored in all registers i, and the gate MUX sequentially selects the multiplication and addition values ​​in the register L and transmits to module B. Inserting an additional register L in the gate MUX can realize the sequential gate of register i and seamless subtask switching, simplify the timing control in the multiplier-adder array, and reduce the complexity.

[0054] In a possible implementation, N modules A can use the same clock i to count the number of multiplication and addition operations (for example, clock 1, clock 2, ..., clock N all use clock 1), and the multiplication of N modules A After the number of addition operations reaches the first pres...

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Abstract

The invention provides a device for reducing precision loss, which comprises at least one module A and at least one module B. The module A performs multiply-add operation, has input X and Y and performs multiply operation to generate a product value XY, and the module A performs accumulation operation on the product value XY and outputs the multiply-add value; and the module B executes the accumulation operation, receives the multiply-add value of the module A, executes the accumulation operation and outputs an accumulated value. The invention also provides a method for reducing precision loss. According to the device and the method, a large batch of multiply-add tasks are split into a plurality of small batches of multiply-add tasks, so that the calculation error of a single-layer neural network can be greatly reduced.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence, in particular to a device and method for reducing precision loss. Background technique [0002] In today's era, artificial intelligence technology is changing with each passing day and developing rapidly, affecting people's production and life in all aspects, and promoting the development and progress of the world. In recent years, researchers have found that neural network algorithms are very effective for processing unstructured data, such as face recognition, speech recognition, image classification and other tasks. With the exponential growth of these unstructured data, there is a huge demand for the computing power of the processor. The traditional central processing unit (CPU) and digital signal processor (DSP) can no longer meet the demand, and there is an urgent need for professional processors customized for neural network algorithms. Developing a special processor for ...

Claims

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Application Information

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IPC IPC(8): G06N3/08
CPCG06N3/082G06N3/08G06N3/04
Inventor 何伟沈杨书齐园园
Owner LYNXI TECH CO LTD
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