A statistical system and method for data state distribution of abnormal chips
A technology of data status and distribution statistics, applied in static memory, instruments, etc., can solve the problems of long test time, high power consumption of equipment, CPU resource occupation, etc., and achieve the effect of shortening the acquisition time
Active Publication Date: 2022-03-18
YANGTZE MEMORY TECH CO LTD
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[0003] In related technologies, the data state distribution of statistical chips requires a large amount of data calculations, and the software logic is complex, and these large amounts of data calculation processes are implemented in a central processing unit (Central Processing Unit, CPU), occupying a large amount of CPU resources , the power consumption of the device is large; in addition, when counting the state distribution of chip data in related technologies, there are a large number of memory access operations, resulting in long test time
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[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the specific technical solutions of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following examples are used to illustrate the present application, but not to limit the scope of the present application.
[0039] In the following description, use of suffixes such as 'module' or 'unit' for denoting elements is only for facilitating the description of the present application and has no specific meaning by itself. Therefore, "module" or "unit" can be used mixedly.
[0040] A Cell of TLC can store 3-bit data, so there are 8 data states in TLC. Usually, the data stored in TLC will be evenly distributed to each data state. Therefore, each Data states are completely independent of each other and do not overlap. However, due to the bit flipping phenomenon, the data ...
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The embodiment of the present application provides a statistical system and method for data state distribution of abnormal chips, wherein the data state distribution statistical system of abnormal chips at least includes: a sampling and comparison module, which is used to compare the expected data under each column address with the corresponding column The address is compared with the read data under different read voltages to obtain the set of error bit information under each read voltage and the column address of the error bit unit corresponding to each error bit information; the signal generation module is used to pass the expected data The data state in the corresponding data state set generates a control signal corresponding to the data state; the selection module is used to filter out the target error bit corresponding to the target column address from the error bit information set according to the control signal and the column address Information, in order to realize the data state distribution of the abnormal chip through the target error bit information.
Description
technical field [0001] The present application relates to the field of semiconductor testing, and relates to but not limited to a system and method for statistical distribution of data status of abnormal chips. Background technique [0002] Flash memory (NAND Flash) can be divided into single-level storage cells (Single-Level Cell, SLC), double-level storage cells (Multi-Level Cell, MLC) and triple-level storage cells (Triple-Level Cell, TLC) through different storage principles , where one memory cell (Cell) of the TLC stores 3 bits (Bit) of data, so there are 8 data states in the TLC. Normally, the data stored in the TLC will be evenly distributed to each data state. However, due to the bit flipping phenomenon, the data state of the stored data will change, so it is particularly important to count the data state distribution of the chip. [0003] In related technologies, the data state distribution of statistical chips requires a large amount of data calculations, and th...
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IPC IPC(8): G11C29/44G11C29/50
CPCG11C29/44G11C29/50G11C2029/5004
Inventor 李康彭聪
Owner YANGTZE MEMORY TECH CO LTD