Data transmission method and device

Abstract

The invention discloses a data transmission method, which is suitable for data transmission between an internal memory of a system-on-chip and an external memory coupled with the system-on-chip; the method is executed by a processor of the system-on-chip, and the method comprises the following steps: adding execution information of at least one data transmission task to be executed to a task queue; sending execution information of a data transmission task in the task queue to the direct access device, so that the direct access device executes the data transmission task; and receiving an interrupt request sent by the direct access device, the interrupt request being suitable for indicating that execution of the data transmission task is completed, so that the processor sends execution information of the next data transmission task in the task queue to the direct access device. The invention also discloses a corresponding data transmission device, the system on chip and the intelligent equipment.

Description

Technical field [0001] The present invention relates to the field of embedded techniques, and more particularly to a data transmission method and apparatus between an internal memory and an external memory of a system. Background technique [0002] With the development of network communication technology, today's society has entered the Internet of Things. Systemon Chip, SOC is a system integrated with modules such as processors, memory, external devices, I / O interfaces, embedded in the Internet of-connected devices for specific functions. In order to meet low-power, low-cost design requirements, the internal storage capacity of on-chip systems is usually smaller, and a large amount of data is stored on an external memory coupled to the on-chip system. [0003] The internal memory is quickly read and written, but the capacity is small; the external memory capacity is large, but the read and write speed is slow. In some application scenarios, data transmission between internal m...

AI Technical Summary

Problems solved by technology

[0005] In this example, since the processor sends the data information required in step d to the DMA device at time t3, the DMA device is in an idle state during the time period t2-t3, and the time for transmitting the data in step d is delayed, causing the processor During the period from t4 to t5, we can only wait for the completion of data transmission, but cannot perform computing tasks, wasting computing resources

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