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Full adder

A technology of full adder and signal, applied in the field of full adder, can solve the problem of high power consumption of full adder

Pending Publication Date: 2021-07-09
北京源启先进微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But the power consumption of the full adder with this structure is high

Method used

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Embodiment Construction

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0039] figure 1 A schematic circuit structure diagram of a full adder is provided for the embodiment of the present application.

[0040] Such as figure 1 As shown, the full adder in this embodiment includes: a first exclusive OR circuit, a second exclusive OR circuit, and a carry circuit.

[0041] The first exclusive OR circuit is used to access the first summation signal and the second summation signal, and the first exclusive OR circuit includes two sets of co...

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Abstract

The embodiment of the invention provides a full adder. The full adder comprises a first exclusive-OR circuit, a second exclusive-OR circuit and a carry circuit; the first exclusive-OR circuit is used for accessing a first summation signal and a second summation signal, and the first exclusive-OR circuit comprises two groups of comparison circuits; a reverse signal of the first summation signal and the second summation signal are respectively connected to two input ends of the second group of comparison circuits, and the second group of comparison circuits output low level when the reverse signal of the first summation signal is not equal to the second summation signal; the output ends of the two groups of comparison circuits are connected and serve as the output end of the first exclusive-or circuit to output a first exclusive-or signal; the second exclusive-or circuit is used for performing exclusive-or calculation on the first exclusive-or signal and the carry input signal and outputting a summation signal; the carry circuit is used for carrying out calculation according to one of the first summation signal and the second summation signal, the carry input signal and the first XOR signal and outputting a carry output signal.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a full adder. Background technique [0002] A full adder, also known as a full-adder, is a circuit that can add and sum two binary numbers. Each bit of a binary number generally corresponds to a one-bit full adder, and a one-bit full adder can handle its own Summing and low-order addition carry, and output the summation result of the original bit and the addition carry of the original bit. [0003] In addition, the full adder can not only complete addition calculations, but also participate in operations such as subtraction, multiplication, and division. It is an important part of processors such as microprocessors and digital signal processors. Therefore, reducing the power consumption of the full adder has a Significance. [0004] Generally, the full adder will use multiple MOS transistors, the source of the MOS transistors will be connected to the power supply VC...

Claims

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Application Information

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IPC IPC(8): H03K19/20
CPCH03K19/20
Inventor 不公告发明人
Owner 北京源启先进微电子有限公司
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