Capacitor network mismatch correction method and device

Abstract

The invention discloses a capacitor network mismatch correction method and device, and the method comprises the steps: 1, obtaining an ideal threshold voltage of a predetermined digital code of an ADC to be corrected according to a predetermined rule; 2, arranging a plurality of capacitors corresponding to the predetermined digital code so as to minimize the error between the threshold voltage of the predetermined digital code and the ideal threshold voltage; 3, executing the step 1 and the step 2 on each digital code in the ADC to be corrected according to the sequence from the high-order digital code to the low-order digital code so as to correct the mismatch of the capacitor network of the ADC to be corrected. According to the invention, the capacitor network mismatch of the ADC can be corrected, so that the precision of the ADC can be improved.

Description

technical field [0001] The invention relates to the field of analog-to-digital converter design, in particular to a correction method and device for capacitance network mismatch. Background technique [0002] In the design of SAR ADC (Successive Approximation Register Analog-to-Digital Converter, successive comparison analog-to-digital converter), the matching degree of the capacitor voltage divider network will largely affect the accuracy of the ADC. However, the errors generated during the chip manufacturing process are difficult to avoid, and the capacitance value is difficult to measure after the manufacturing is completed. At present, the following technologies are mainly used to improve the accuracy of ADC: [0003] (1) Use laser trimming technology to make the matching of weight capacitor or weight resistance network better. [0004] (2) In the layout design, in addition to designing the unit capacitor, design many small capacitors or resistors near the unit capacit...

AI Technical Summary

Problems solved by technology

[0006] However, technology (1) has the following problems: the use of laser trimming requires additional process costs

[0007] Technology (2) has the following problems: the complexity of the layout design is increased, and due to the limitation of manufacturing accuracy, it is difficult to manufacture very small capacitors to make up for the error (the standard deviation of the capacitor in the COMS process is generally below 1%)

[0008] Technology (3) has the following problems: an additional DAC needs to be added to the circuit design to compensate for errors caused by capacitance mismatch

This results in a DAC requiring very high precision, which is difficult to achieve

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