Hybrid short circuit failure mode preform for power semiconductor devices

Abstract

A power semiconductor module comprises a base plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

Description

technical field [0001] The invention relates to the field of power semiconductor modules comprising a substrate, a wide bandgap semiconductor chip arranged on the substrate, a preform arranged on the wide bandgap semiconductor chip, and a pressing element configured to apply pressure to the preform . More specifically, the present invention relates to hybrid preforms providing short-circuit failure mode (SCFM) capability in such power semiconductor modules. Background technique [0002] In high power applications, a series connection of multiple power semiconductor modules is often required to meet high voltage requirements. Due to the series connection, the failure of a single module can lead to the failure of the entire device. Power semiconductor modules which become permanently conductive in the event of failure of their semiconductor chips therefore have great advantages in such a series connection. This capability is known as Short Circuit Failure Mode (SCFM). [0...

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Problems solved by technology

There are also reliability issues regarding mechanical stability, because when the area of ​​the preform is significantly smaller than the area of ​​the SiC chip, the mechanical stress (pressure = load / area) is concentrated on the small area of ​​the SiC chip, which increases the risk of damage to the SiC chip. risks of

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