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Method of forming semiconductor structure and semiconductor structure

A conductor structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc.

Pending Publication Date: 2021-08-03
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is difficult to provide a partially depleted SOI field effect transistor and a fully depleted SOI field effect transistor within a SOI substrate in which the top semiconductor layer as a whole has the same thickness.

Method used

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  • Method of forming semiconductor structure and semiconductor structure
  • Method of forming semiconductor structure and semiconductor structure
  • Method of forming semiconductor structure and semiconductor structure

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0161] The ensuing disclosure provides many different implementations or examples for achieving different features of the presented subject matter. Specific embodiments of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the ensuing description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features form direct contact, and may also include Additional features may be formed between them, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat numbers and / or letters in various embodiments. Such repetition is for the sake of simplicity and clarity, and the repetition itself does not imply a relationship between the various embodiments and / or configurations discussed.

[0162] In addition, relative terms in space, such as "below", "bel...

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PUM

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Abstract

A method of forming a semiconductor structure and a semiconductor structure. Formation of semiconductor-on-insulator (SOI) field effect transistors including a plurality of base regions having different thicknesses may be performed by selectively thinning a region of the top semiconductor layer while avoiding thinning an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer. A patterned oxidation barrier mask or etch mask may be used to prevent oxidation or etch of the additional portion of the top semiconductor layer. A plurality of shallow trench isolation structures may be formed before or after the selective thinning process step. Multiple field effect transistors with different depletion region configurations may use multiple thicknesses of multiple patterned portions of the top semiconductor layer. For example, a partially depleted SOI field effect transistor and a fully depleted SOI field effect transistor may be provided.

Description

technical field [0001] The present disclosure relates to semiconductor devices including a plurality of semiconductor-on-insulator field effect transistors, and to methods of forming such semiconductor devices. Background technique [0002] Semiconductor-on-insulator (SOI) field effect transistors are formed by providing a semiconductor-on-insulator substrate comprising a stack, from bottom to top: a handle substrate, an insulating layer, and a top semiconductor layer, and via A plurality of shallow trench isolation structures, various doped semiconductor regions, and a plurality of gate stack structures are formed in or over them. In this way, each SOI field effect transistor has the same thickness. The device characteristics of the MOSFETs can be determined by the thickness of the MOSFETs. For example, if the depletion region within a floating body region does not extend across the entire floating body region, a partially depleted SEFIFET may be formed. Alternatively, f...

Claims

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Application Information

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IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/8234H01L27/088H01L21/76281H01L29/7869H01L29/0653H01L27/1203H01L21/76224H01L21/76227H01L21/76229H01L21/76232H01L21/7624H01L21/76264H01L21/76283H01L27/1233H01L29/786H01L29/78696
Inventor 辛格·古尔巴格王柏仁庄坤苍
Owner TAIWAN SEMICON MFG CO LTD