System and method for reading and writing image of control path in switching chip

Abstract

This application discloses a mirror read and write system for control channels in a switch chip. In a switch chip that includes multiple parallel replication packet processing pipeline architectures, the table entries of multiple pipelines are simultaneously configured by reading mirror images and writing mirror images, and the control channels Receive the read responses of all pipelines and the write responses of the target address pipelines, ensuring that the multiple parallel packet processing pipelines have no difference in the configuration and posting items, thereby improving the packet switching capability of the switching chip containing multiple packet processing pipelines. Compared with the existing technology, it can effectively realize the synchronous distribution of configuration between parallel packet processing pipelines, so that the packet data can run in parallel without perception on multiple pipelines, realize the configuration and management without difference between multiple pipelines, and ensure the control path The efficiency and stability of the data path. The method for reading and writing the image of the control path in the switching chip provided by the present invention also solves the corresponding technical problems.

Description

technical field [0001] The present application relates to the technical field of switch chip design, in particular to a system and method for reading and writing a control path image in a switch chip. Background technique [0002] As the demand for packet switching capability of the switch chip increases, the switch chip integrates more high-speed interfaces. Packet data enters and aggregates from the high-speed interface, and then enters multiple parallel packet processing pipelines inside the chip to realize L2-L4 layer packet processing. , and then forwarded through the high-speed interface. With the increase of the number of high-speed interfaces and interface bandwidth, the interface convergence capability and the processing capability of the pipeline restrict the packet switching capability of the switch chip. By duplicating the packet processing pipeline in the chip, multiple pipelines can run in parallel, which can greatly improve the switching chip. packet switchin...

AI Technical Summary

Problems solved by technology

[0003] However, in the prior art, the control path read and write strategy of multiple parallel packet processing pipelines is generally as follows: during the reading process, the control path issues the read address, each receiving module receives the read request, and checks whether the address matches. , the read request continues to the next module for detection, so there is a time difference between read requests for two different modules

During the writing process, the control channel writes configurations to the two modules on the chip at the same time. When both are successfully written, the control channel considers that the write request has been correctly responded. When one of the writing configurations fails, the control channel will initiate a write request again. , until the data is successfully written into the two modules that need to be configured; you can also use the sequential writing process, first write one of the modules, and then write the other module, which will cause a time difference between the write requests of the two different modules

As a result, the distribution configuration of table items between different pipelines is not synchronized, which restricts the packet switching capability of the switching chip

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