Gate structure and preparation method thereof, and transistor and preparation method thereof

A gate structure and gate trench technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of high gate structure preparation cost and low production capacity

Active Publication Date: 2021-09-14
SEMICON MFG ELECTRONICS (SHAOXING) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a grid structure and its preparation method to solve the current problems of high manufacturing cost and low production capacity of the grid structure

Method used

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  • Gate structure and preparation method thereof, and transistor and preparation method thereof
  • Gate structure and preparation method thereof, and transistor and preparation method thereof
  • Gate structure and preparation method thereof, and transistor and preparation method thereof

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preparation example Construction

[0029] To this end, the present invention provides a preparation method of a gate structure, which can still prepare a gate structure with a smaller size based on a lower lithography precision, which is beneficial to increase the production capacity and reduce the cost. For details, please refer to figure 1 As shown, the preparation method of the gate structure includes the following steps.

[0030] Step S100, a first material layer and a second material layer are formed on the substrate in sequence, a first window is opened in the second material layer, and the dielectric constants of the first material layer and the second material layer are the same. lower than the dielectric constant of silicon nitride.

[0031] Step S200, forming a mask spacer on the sidewall of the first window, and defining a second window by the mask spacer.

[0032] Step S300, removing the portion of the first material layer exposed to the second window to form a third window in the first material l...

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Abstract

The invention provides a gate structure and a preparation method thereof, and a transistor and a preparation method thereof. A mask side wall is formed on the side wall of a first window in a second material layer to define a second window with a smaller size, and the second window can be further copied into the first material layer to define the size of a gate pin of a gate structure. Therefore, according to the preparation method provided by the invention, a grid length with a smaller size can be defined based on a low-precision photoetching machine, the problem of process limitation of a traditional photoetching machine is solved, and the economic benefit is effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a gate structure and a preparation method thereof, a transistor and a preparation method thereof. Background technique [0002] With the rapid development of mobile communication technology, the application of high-frequency and high-power devices is becoming more and more extensive, and the requirements for high-frequency performance are also getting higher and higher. In order to obtain high frequency characteristics, on the one hand, materials with high mobility can be used, and on the other hand, reducing the gate length is also an important means, but when the gate length decreases, the gate resistance will increase, which will lead to an increase in the noise figure and The maximum oscillation frequency is reduced, etc. In order to reduce the gate length without increasing the resistance, a T-shaped gate structure is usually used. [0003] At present, the T-type ga...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L29/423H01L29/778
CPCH01L21/28H01L29/42316H01L29/778
Inventor 郑茂波刘国安
Owner SEMICON MFG ELECTRONICS (SHAOXING) CORP
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