Operational circuit system based on hardware acceleration and chip

Abstract

The invention discloses an operational circuit system based on hardware acceleration and a chip. The operational circuit system comprises a square root extraction iteration module and a reciprocal iteration module. The square root extraction iteration module is used for multiplying a preset number to be subjected to square root extraction by a reciprocal result which is output by the reciprocal iteration module and meets a preset convergence condition when the end mark of the reciprocal iteration operation is valid and the end mark of the square root extraction iteration operation is invalid so as to carry out the square root extraction iteration operation with preset precision. The reciprocal iteration module is used for controlling the reciprocal result output by the reciprocal iteration module in the last-level reciprocal iteration operation and the square root result output by the square root extraction iteration module in the last-level square root extraction iteration operation in the current-level reciprocal iteration operation when the enabling mark of the reciprocal iteration operation is valid, and obtaining the reciprocal result which is output by the reciprocal iteration module and meets a preset convergence condition. The hardware processing of the reciprocal iterative operation formula and the square root extraction iterative operation is completed, and the use of a divider is avoided.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a computing circuit system and chip based on hardware acceleration. Background technique [0002] The square root operation is widely used in digital circuits. In the prior art, the methods generally used in the square root operation include real function approximation method, Newton iteration method and other calculation methods. Among them, the real function approximation method has low precision, and the Newton iteration method Involving the calculation of division, the realization of the calculation process of the two requires a lot of hardware resources. In particular, the currently commonly used floating-point division operation is relatively complicated. The usual method is to use multiple subtraction iterations to complete it. The hardware resource overhead is large, and the completed clock cycle is long. It is not suitable for cost-sensitive and high requirem...

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Problems solved by technology

[0002] The square root operation is widely used in digital circuits. In the prior art, the methods generally used in the square root operation include real function approximation method, Newton iteration method and other calculation methods. Among them, the real function approximation method has low precision, and the Newton iteration method Calculation involving division, the realization of the calculation process of the two requires a lot of hardware resources

In particular, the currently commonly used floating-point division operation is relatively complicated. The usual method is to use multiple subtraction iterations to complete it. The hardware resource overhead is large, and the completed clock cycle is long. It is not suitable for cost-sensitive and high requirements for calculation delay. The application scenario of batch processing data of sensors restricts the application range of square root calculation

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