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Implementation method and system of L1cache uncommit_oldest priority strategy

A prioritization strategy and system implementation technology, applied in resource allocation, program control design, instrumentation, etc., can solve problems such as no processing, command retire delay, CPU not working normally, etc., to achieve the effect of improving stability and reducing deadlock

Pending Publication Date: 2021-10-01
GUANGDONG STARFIVE TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the prior art, there is no special treatment for the uncommit_oldest instruction, resulting in the uncommit_oldest instruction not getting a timely response, and the instruction retire being delayed, which has a great impact on the performance of the CPU
[0003] If the instruction has a deadlock situation, there is no processing, so the CPU cannot work normally

Method used

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  • Implementation method and system of L1cache uncommit_oldest priority strategy
  • Implementation method and system of L1cache uncommit_oldest priority strategy

Examples

Experimental program
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Embodiment 1

[0029] refer to figure 1 As shown, this embodiment discloses a system for implementing an L1cache uncommit_oldest priority strategy, including:

[0030] The ename module is used to rename the destination register of the instruction; at the same time, it saves the mapping relationship between the architectural register and the physical register;

[0031] The dispatch module is used to distribute instructions to different datapaths according to the type of instructions;

[0032] lsu module, used for load and store command datapat;

[0033] The ROB module is used to maintain the sequential submission of instructions, while maintaining the mapping table of non-speculative architectural registers and physical registers.

[0034] In this embodiment, the ename module sends instructions to the dispatch module and the ROB module.

[0035] In the ename module of this embodiment, when the instruction in the ROB is graduated, the physical register is released, and the free list of the ...

Embodiment 2

[0041] Such as figure 2 As shown, this embodiment discloses a basic block diagram of lsu. It can be clearly seen in this block diagram that the arbiter inside the queue: load_queue, store_queue and miss queue all contain multiple entry items. There may be so many entry items at the same time If multiple entry items want to be added to the pipeline, arbitration is required at this time, and arbitration has a strategy. In this embodiment, the oldest entry is selected from among the many entries.

[0042] Arbiter between different queues in this embodiment: between different queues, if the requested information also includes complete age information, select the oldest one according to the age information, which will make the implementation tense, but the request information contains a Information to indicate that the current instruction is released as the uncommit_oldest flag. If the flag is 1, the instruction has the highest priority in the arbiter among different queues.

Embodiment 3

[0044] This embodiment discloses a method for implementing the L1cache uncommit_oldest priority policy. The method includes a flag in the request information to indicate that the current instruction is released as uncommit_oldest. If the flag is 1, the instruction is arbiter among different queues. In LDQ, STQ, and LMQ, the uncommit_oldest command is given the highest priority in arbitration, which allows the command to retire as soon as possible, thereby ensuring that the uncommit_oldest command gets a timely response.

[0045] In this embodiment, for the uncommit_oldest command, if the time limit exceeds the threshold and has not been put into the pipeline, the pipeline is forced to be put into the pipeline.

[0046]To sum up, the uncommit_oldest of the present invention has the highest priority in all arbitrations, allowing the command to retire as soon as possible, so that LDQ, STQ, ROB, PHY freelist, etc., which can only be released with the command retire, can be released...

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Abstract

The invention relates to the technical field of microprocessors, in particular to an implementation method and system of an L1cache uncommit_oldest priority strategy. The system comprises an ename module, a dispatch module, an lsu module and an ROB module. Request information comprises a mark indicating that a current instruction is released to be uncommit_oldest, if the mark is 1, the instruction has the highest priority in arbiters between different queues, the highest priority is given in arbitration for the uncommit_oldest instruction in LDQ, STQ and LMQ, the instruction can be retired as soon as possible, then it is ensured that the uncommit_oldest instruction is responded in time, if the uncommit_oldest instruction is not accessed to the pipeline after a certain period of time, the instruction is forced to be accessed to the pipeline, in this way, deadlock can be effectively reduced, and the stability of the system is improved.

Description

technical field [0001] The present invention relates to the technical field of microprocessors, in particular to a method and system for realizing an L1cache uncommit_oldest priority strategy. Background technique [0002] In the prior art, there is no special treatment for the uncommit_oldest instruction, resulting in the uncommit_oldest instruction not getting a timely response, and the instruction retire being delayed, which has a great impact on the performance of the CPU [0003] If the instruction has a deadlock situation, there is no processing, so the CPU cannot work normally. [0004] Therefore, this paper proposes a method and system for implementing the L1cache uncommit_oldest priority policy so that uncommit_oldest has the highest priority in all arbitrations, allowing the command to retire as soon as possible, so that LDQ, STQ, ROB, PHY freelist, etc. can only be released with the command retire Resources are released as quickly as possible. [0005] For the u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/50
CPCG06F9/30098G06F9/5022G06F9/5038G06F2209/5021
Inventor 李长林刘磊
Owner GUANGDONG STARFIVE TECH LTD
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